Samsung Electronics Co., Ltd.

Byoungsul Kim

Hokyong Lee

Joonmin Park

Youngsan Kang

Hyunsoo Shim

Hwajin Jung

Yongjoo Choi

Dongjun Kim

Daehyun Kwon

Jun-Ho Jo

Byung Yo Lee

Kyu-Min Park

Kideok Han

Byungyo Lee

Yejin Jo

Myong-Seob Song

Hakyong Lee

Sungtack Hong

Byungmin Choi

An operating method of a storage device including a non-volatile memory is provided. The operating method includes: receiving a first source voltage through a first voltage signal pin; based on the first source voltage different from a target voltage of the storage device, controlling the first source voltage to the target voltage; receiving a command, which indicates an information request associated with an operation voltage of the storage device, from a host; transmitting a response, which corresponds to the information request, to the host by using the storage device; receiving a second source voltage which has a voltage level different from the first source voltage, through the first voltage signal pin; and providing the second source voltage to the non-volatile memory.

Operating method of storage device, operating method of host, and storage system including the storage device and the host

A universal flash storage (UFS) device includes a UFS data lane comprising a first UFS lane for a first direction in which data is output to a UFS host, a second UFS lane for a second direction in which data is received from the UFS host, and bidirectional UFS lanes capable of switching the first direction and the second direction according to an operation mode. A UFS device controller switches a data transmission direction of the bidirectional UFS lanes, based on a control signal indicating the operation mode.

UFS device, method of operating the UFS device, and system including the UFS device

Disclosed is a user system which includes a first device and a second device, which share a shared voltage, and a power management integrated circuit (PMIC) generating the shared voltage. An operation method of the user system includes performing a first operation of the first device, determining whether a second operation of the second device is to be performed while the first device performs the first operation, based on an operation profile, and when it is determined that the second operation of the second device is to be performed while the first device performs the first operation, changing a power mode of the PMIC from a first power mode to a second power mode, before the second device performs the second operation. The PMIC generates the shared voltage based on the first power mode or the second power mode.

User system including first and second devices sharing shared voltage and power management integrated circuit generating shared voltage, and operation method thereof

A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.

Memory chip having on-die mirroring function and method for testing the same

An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.

Electronic device, system-on-chip, and operating method thereof

A memory system including a first central processing unit, a first memory module connected to the first central processing unit by a first channel, a second memory module connected to the first central processing unit by a second channel, and a third memory module connected to the first central processing unit by a third channel may be provided. Each of the first memory module, the second memory module, and the third memory module may be configured to write the same data in a data area thereof and a mirroring data area thereof in response to an address in a mirroring mode.

Memory, memory system having the same and operating method thereof

A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, tire package test, tire module test or the mounting test is failed.

A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a mode control signal generator. When a real entry signal is detected, the entry signal determinator generates an entry determination signal and a test mode control signal is obtained from the mode control signal generator.

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Suwon-si, South Korea

Byoungsul Kim