Samsung Electronics Co., Ltd.

Soulbrain Co., Ltd.

Byoungmoon Yoon

Kyunghyun Kim

Hoon Hee Han

Kyounghwan Kim

Yongsun Ko

Jihoon Jeong

Sang Won Bae

Daehong Eom

Se-Ho Cha

Jinuk Lee

Jaewan Park

ChangSup Mun

Junghun Lim

Seonghwan Park

Chanjin Jeong

Yanghwa Lee

Young-taek Hong

Hyo-Jung Kim

Young Taek Hong

JongHeun Lim

Myungjung Pyo

JaHyung Han

Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Compositions for etching

Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Compositions for etching and methods of forming a semiconductor device using the same

According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.

Methods of manufacturing three-dimensional semiconductor devices

Growing community of inventors

Hwaseong-si, South Korea

Byoungmoon Yoon