Samsung Electronics Co., Ltd.

S-printing Solution Co., Ltd.

Byoungil Lee

Joonhee Lee

Yujin Seo

Euntaek Jung

Joongshik Shin

Hyunmog Park

Seonghun Jeong

Seong-hun Jeong

Bosuk Kang

Jimo Gu

Subin Kang

Seul Gee Lee

Seong Soon Cho

Dongseog Eun

Bonghyun Choi

Sejie Takaki

Seungwoo Nam

Kyung-Jun Shin

Changdae Jung

Hyunkook Lee

Sehoon Lee

Jongchoon Kim

Uichoon Lee

Jungwoo Son

Disclosed are three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same. The device includes a substrate including a cell array region and an extension region, stack structures extending in a first direction and including gate electrodes stacked on the substrate, vertical structures penetrating the stack structures on the cell array region, a mold structure on a portion of the extension region, a first support structure extending in the first direction between the stack structures, second support structures penetrating the stack structures on the extension region and spaced apart in a second direction from the first support structure, and a third support structure surrounding the mold structure in a plan view. Respective top surfaces of ones of the second support structures and a top surface of the third support structure is higher than a top surface of ones of the vertical structures.

Three-dimensional semiconductor memory device and electronic system including the same

A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

Three-dimensional semiconductor memory devices

A semiconductor device includes a peripheral circuit structure including a first substrate and circuit elements on the first substrate; and a memory cell structure including a second substrate on the first substrate, a first horizontal conductive layer on the second substrate, a second horizontal conductive layer on the first horizontal conductive layer, gate electrodes spaced apart from each other and stacked on the second horizontal conductive layer, channel structures penetrating through the gate electrodes, and separation regions penetrating the gate electrodes, extending, and spaced apart from each other. The semiconductor device has a through-wiring region including a through-contact plug electrically connecting the memory cell structure and the peripheral circuit structure, the separation regions include first separation regions adjacent to the through-contact plug, and the first separation regions penetrate through the second horizontal conductive layer and are spaced apart from the first horizontal conductive layer.

Semiconductor devices and data storage systems including the same

A three-dimensional nonvolatile memory device includes: a substrate including a cell area and an extension area having a staircase structure; a vertical structure on the substrate; a stacking structure having electrode layers and interlayer insulating layers on the substrate; a separation insulating layer on the substrate and separating the electrode layers; and a through-via wiring area adjacent to the cell or extension area and having through-vias passing through the substrate, wherein the cell area includes a main cell area in which normal cells are arranged and an edge cell area, the separation insulating layer includes a main separation insulating layer in the main cell area and an edge separation insulating layer in the edge cell area, and a lower surface of the main separation insulating layer is higher than the upper surface of the substrate and has a different depth than a lower surface of the edge separation insulating layer.

Three-dimensional nonvolatile memory device and a method of fabricating the same

A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

Semiconductor device

A vertical memory device includes channels on a substrate, a channel connecting pattern, gate electrodes, and an etch stop pattern and a blocking pattern sequentially stacked. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connecting pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The gate electrodes are spaced apart from each other in the first direction on the channel connecting pattern, and extend in the second direction to surround the channels. The etch stop pattern and the blocking pattern are sequentially stacked in a third direction parallel to the upper surface of the substrate and crossing the second direction on an end portion of the channel connecting pattern in the third direction, and include different materials from each other.

Methods of manufacturing vertical memory devices

3D semiconductor memory devices may include a horizontal structure that may be on an upper surface of a substrate and may include first and second horizontal patterns sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode may have first inner sidewalls facing each other with the separation structure interposed therebetween. The second horizontal pattern may have second inner sidewalls facing each other with the separation structure interposed therebetween. A maximum distance between the first inner sidewalls in the first direction may be less than a maximum distance between the second inner sidewalls in the first direction.

Vertical memory devices and methods of manufacturing the same

A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

Semiconductor memory device

Semiconductor memory device and method of fabricating the same

An image forming device is provided. The image forming device may include a transfer belt to move in a preset direction, a plurality of image generators to respectively generate a toner image on the transfer belt, and a controller to output an image generation signal to each of the plurality of image generators such that the plurality of image generators respectively generate a toner image. A plurality of toner images generated using the plurality of image generators are arranged on the transfer belt in parallel to each other, and an arrangement order of the plurality of toner images is identical to an arrangement order of the plurality of image generators.

Image forming device and control method for generating a plurality of toner images

A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.

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Seoul, South Korea

Byoungil Lee