Samsung Electronics Co., Ltd.

Byounggon Kang

Dalhee Lee

Changbeom Kim

Ha-Young Kim

Eun-Hee Choi

Minji Kim

Jintae Kim

Giyoung Yang

Subin Jin

Taejun Yoo

Seunghyun Yang

Yongeun Cho

Wookyu Kim

Taejung Seol

Jaebeom Yang

An integrated circuit includes plural standard cells performing a same function. The standard cells include a first standard cell and a second standard cell, and the first standard cell and the second standard cell are to the same as each other in terms of an arrangement of internal conductive patterns and are different from each other in terms of a position of a via formed over a gate line through which an input signal is input.

Integrated circuit including standard cell and method of designing the same

A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.

Asymmetric NAND gate circuit, clock gating cell and integrated circuit including the same

A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.

Flip-flops and scan chain circuits including the same

A flip-flop circuit includes a first master latch circuit transmitting an inverted signal of an input signal received from an external device to a first node and transmitting an inverted signal of a signal of the first node to a second node, according to a first control signal having a first logic level or a second control signal having a second logic level, a first slave latch circuit transmitting an inverted signal of a signal of the second node to a third node according to the first control signal having the second logic level or the second control signal having the first logic level, a first output inverter generating a first output signal by inverting a signal of the third node, and a first control signal generation circuit generating the first control signal and the second control signal based on a clock signal and the signal of the first node.

Flip-flop circuit including control signal generation circuit

A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode.

Semiconductor device

A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

High-speed flip flop circuit including delay circuit

A semiconductor device is provided. The semiconductor device includes power supply lines extending in a first direction; first transistors, each of which is formed in a first region and has a first threshold voltage; and second transistors, each of which is formed in a second region and has a second threshold voltage higher than the first threshold voltage. One of the plurality of power supply lines is interposed between the first region and the second region, the first transistors implement a first portion of a multiplexer, a clock buffer and a first latch that are disposed on a data path, the second transistors implement a second portion of the multiplexer circuit and a second latch that are disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed in a common location along the first direction.

A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

Semiconductor device including standard cell

An integrated circuit may include a clock gating cell based. The clock gating cell may include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set reset (SR) latch by being cross-coupled, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and an activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing a pull-up or a pull-down of a first node at which the first signal is generated.

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Seoul, South Korea

Byounggon Kang