Samsung Electronics Co., Ltd.

Byoung Young Ahn

Yang Seok Ki

Inseok Stephen Choi

Young-Ho Park

Sungkug Cho

Stephen Choi

A storage device is described. The storage device may store data in a storage memory, and may have a host interface to manage communications between the storage device and a host machine. The storage device may also include a translation layer to translate addresses between the host machine and the storage memory, and a storage interface to access data from the storage memory. An in-storage monitoring engine may determine characteristics of the storage device, such as latency, bandwidth, and retention.

Method and apparatus for storage device latency/bandwidth self monitoring

A storage device includes an application container containing applications, each of which runs in one or more namespaces; flash memory to store data; a host interface to manage communications between the storage device and a host machine; a flash translation layer to translate a first address received from the host machine into a second address in the flash memory; a flash interface to access the data from the second address in the flash memory; and a polymorphic device kernel including an in-storage monitoring engine. The polymorphic device kernel receives a plurality of packets to an application running on the storage device and provides the flash interface based on a namespace associated with the plurality of packets. The in-storage monitoring engine determines a dynamic characteristic of the storage device at run-time based on a matching of a profiling command received from the host machine in a performance table.

A storage device includes a controller that receives a value corresponding to data stored in a memory and a key to be referenced to identify the value from a host. In addition, the controller manages partial key-value mapping information indicating a correspondence relationship between a partial key and a value address, and returns information to the host in response to a host request. The information corresponds to a key that includes a same character as a character at a specific position of the received key. The controller to determine the information by determining a partial region of the memory that stores the data based on the partial key-value mapping information and performing a read operation on the partial region to obtain an entire key including the partial key.

Device for performing iterator operation in database

Embodiments are disclosed for adaptive power reduction for a solid-state storage device to dynamically control power consumption. Aspects of the embodiments include receiving a power limit command from a host; receiving power consumption feedback; using the power limit command and the power consumption feedback to calculate a new degree of parallelism; using the new degree of parallelism to control one or more of: i) processor parallelism, including activation of different numbers of processors, ii) memory parallelism, including memory pool length; and iii) nonvolatile memory parallelism, including activation of different numbers of nonvolatile memory devices.

Method and apparatus of dynamic parallelism for controlling power consumption of SSDs

A storage device () is described. The storage device () may store data in a storage memory (), and may have a host interface () to manage communications between the storage device () and a host machine (). The storage device () may also include a translation layer () to translate addresses between the host machine () and the storage memory (), and a storage interface () to access data from the storage memory (). An in-storage monitoring engine () may determine characteristics () of the storage device (), such as latency (), bandwidth (), and retention ().

A system for answering queries regarding a system topology and local storage information in a data center is described. The system may include reception logic and transmission logic that may receive and send data, respectively. Among the data that may be received and sent are queries and responses. The system may have storage for a storage graph, which may include nodes and multi-weight edges. A storage distance predictor may use the storage graph to generate the responses to the queries.

Method and apparatus for predicting storage distance

A Tenant-Aware Storage-Sharing Engine (TASTE) () is described. The TASTE () may include storage () for information about a set of available storage devices () at a data center (). A reception logic) may receive storage device requirements () from a tenant (). Selection logic () may then select a subset of the available storage devices () that satisfies the storage device requirements) of the tenant ().

Method and apparatus for tenant-aware storage sharing platform

An embodiment includes a system, comprising: a processor; a plurality of memories; and a control circuit coupled to the processor and the memories, and configured to: receive a power limit; measure a power consumption of the processor and the memories; and iteratively change a plurality of operating parameters of the processor and the memories to optimize an objective function associated with the system to operating states where the power consumption is less than or equal to the power limit.

System and method for controlling power consumption

A multi-level cache system may include a server with a processor and memory. The memory may include a database cache system for use with a distributed database system. The server may also include a Solid State Drive that may include a key-value store and a second storage device that may store a backend database. The key-value store may act as a second level cache to the database cache system.

System and methods for multi-level key-value store

In a multi-level cache system, a logic may be responsible for calculating the appropriate sizes for a database cache and a key-value store. Reception circuitry may receive a hit rate for the database cache, a reuse distance for the key-value store, and a user-selected quality of server. An adaption calculator may then calculate a target size for the database cache and a target size for the key-value store. Transmission circuitry may then transmit the target size for the database cache and the target size for the key-value store for use in the multi-level cache system.

System and methods for adaptive multi-level cache allocation for KV store

A solid state memory system includes: an interface circuit; a device processor, coupled to the interface circuit, configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command; a non-volatile memory array coupled to the interface circuit; and a power manager unit, coupled between the device processor and the non-volatile memory array, configured to alter an operating configuration of the non-volatile memory array to meet the requirement of the dynamic power limit command.

Solid state memory system with power management mechanism and method of operation thereof

A memory device and a method for rescheduling memory operations is disclosed. The method includes receiving memory operations for memory arrays of a memory device; storing the memory operations in queues associated with the memory array; estimating power consumption for each of the memory operations queued in the queues based on a power model; determining that a memory operation causes an estimated power consumption of the memory device to be exceeded over an allowable power budget within a first time window; determining a candidate memory operation in the queues that is scheduled to operate in a second time window after the first time window, wherein the candidate memory operation has less power consumption than the memory operation according to the power model; and dynamically reordering the memory operations in the queues and generating rescheduled memory operations by reordering the memory operation out of the first time window and reordering the candidate memory operation into the first time window.

Dynamic non-volatile memory operation scheduling for controlling power consumption of solid-state drives

A computing system includes a memory storage unit, having memory blocks, configured as a memory cache to store values of key-value pairs; and a device control unit, coupled to the memory storage unit, configured to: identify eviction targets from key-value eviction candidates in a key-value registry based on an eviction policy; calculate an associated eviction count of associated eviction candidates within the same instance of the memory blocks as the eviction targets; select an erase block as the memory blocks associated with the highest value of the associated eviction count; and interface with the memory storage unit to perform an erase operation on the erase block.

Computing system with cache management mechanism and method of operation thereof

A memory device and a method for rescheduling memory operations for dynamically controlling power consumption of the memory device is disclosed. The method includes receiving a plurality of memory operations for a plurality of memory arrays of a memory device via a memory channel; storing the plurality of memory operations in a plurality of queues associated with the memory array; receiving a power budget associated with the plurality of memory arrays; determining one or more candidate memory operations in the plurality of queues to meet the power budget for a time window; dynamically rearranging the plurality of memory operations in the plurality of queues and generating rescheduled memory operations that meet the power budget for the time window; and fetching the rescheduled memory operations to the plurality of memory arrays.

Growing community of inventors

San Jose, CA, United States of America

Byoung Young Ahn