Samsung Electronics Co., Ltd.

Byoung-sul Kim

Jun-Ho Jo

Kwan-yong Jin

Sung-taek Hong

Sang-Hoon Lee

Hak-Yong Lee

Seung-Hee Lee

Joon-hee Lee

Kwang-Won Park

Sang-hoon Lee

Kwang-Hee Lee

Jung-Kuk Lee

Hee-joo Choi

Kyu-Min Park

Kwan-Yong Jin

Jae-in Song

An electronic system electronic device includes: an internal battery, an external battery, a memory and a plurality of function modules. The internal battery is configured to generate a first power signal. The external battery is configured to be separated from the electronic device, and to generate a second power signal. The memory is configured to operate based on the first power signal. The plurality of function modules are configured to operate based on the second power signal.

Electronic systems and electronic devices

An electronic system electronic device includes: an internal battery, an external battery, a memory and a plurality of function modules. The internal battery is configured to generate a first power signal. The external battery is detachably attached to the electronic device, the external battery configured to generate a second power signal. The memory is configured to operate based on the first power signal. The plurality of function modules are configured to operate based on the second power signal.

Provided are an application processor and a semiconductor system including the same. The semiconductor system includes the application processor, which may include a first register value and of which an operation is controlled by the first register value. The semiconductor system also includes a semiconductor device, which may include a second register value and of which an operation is controlled by the second register value, and a memory storing a third register value that is a copy of the first register value and a fourth register value that is a copy of the second register value. If the stored third register value is changed, the changed third register value is mapped onto the first register value of the processor, and if the fourth register value is changed, the changed fourth register value is mapped onto the second register value.

Application processor and semiconductor system including the same

A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.

Memory device and memory system including the same

Provided are a semiconductor package, a semiconductor memory module including the semiconductor package, and a system including the semiconductor memory module. The semiconductor package may include a plurality of main terminals arranged on a surface of the semiconductor package with constant intervals, and the plurality of main terminals may include terminals of a first set including a plurality of input/output terminals to which test signals may be input, and terminals of a second set including a plurality of input/output terminals to/from which signals other than the test signals may be input/output.

Semiconductor packages

A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not accessible to users of the data storage cells, and increasing an erase count stored in an erase count storing region of the hidden cell corresponding to at least one erased data storage cell when the at least one data storage cell is erased.

Method and apparatus for managing erase count of memory device

A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.

Semiconductor memory device having mount test circuits and mount test method thereof

Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters and a comparator. Each of the counters counts the number of data output signals in the same logic state, among the data output signals outputted from each memory of the memory modules, and outputs a count signal. The comparator compares the count signal outputted from each of the counters and outputs a comparison signal corresponding to a defect of the memory modules. According to the test system, defects in a memory module can be accurately detected and a possibility of an error in the detection can be reduced when a plurality of memory modules are tested, as compared to conventional test systems.

Test system for conducting parallel bit test

A semiconductor memory device and an operation control method thereof are provided. The method may comprise executing a control such that a precharge operating mode and an active operating mode may be successively performed in response to one pre-active command, thereby reducing the current consumption and loading of the system, and thus, enhancing system performance.

Semiconductor memory device and operation control method thereof

A redundancy circuit for use with a semiconductor memory device is provided. The redundancy circuit includes input address buffers for storing input address bits; fuse boxes for storing repair address bits; a comparator for comparing the input address bits stored in the input address buffers with the repair address bits stored in the fuse boxes; and a redundancy enable determiner for determining whether a redundant memory cell is to be applied to the memory device according to a comparison result of the comparator.

Growing community of inventors

Suwon-si, South Korea

Byoung-sul Kim