Samsung Electronics Co., Ltd.

Soulbrain Co., Ltd.

Byoung-Moon Yoon

Kyung-Hyun Kim

Yong-Sun Ko

Won-Jun Lee

Tae-Hyun Kim

Ji-hong Kim

Jun-Youl Yang

Myung-Jung Pyo

Hyo-Jung Kim

In-Seak Hwang

Jong-Heun Lim

Dae-hong Eom

Hoon Hee Han

Cheol-Woo Park

Ki-Hyun Hwang

Han-Mei Choi

Sang-rok Hah

In-Sun Park

Seung-Ho Park

In-seak Hwang

Joon-Sang Park

Jae-Wan Park

Kwang-Wook Lee

Dong-Chul Yoo

Won-sang Song

Dae-Hyuk Chung

Chan-Jin Park

Jin-Uk Lee

Jeong-Hwan Yang

Se-Ho Cha

Chang-Sup Mun

Chung-Ki Min

Ki-Hyung Ko

Jeong-Lim Nam

In-joon Yeo

Young-taek Hong

Young-Ok Kim

Dae-Keun Kang

Chang-Gil Ryu

Kyung-hyun Kim

Tae-Heon Kim

Jung-hun Lim

Hyun-Ho Cho

Yong-Myung Jun

In-Joon Yeo

Tae-eun Kim

Keon-Young Kim

Hea-Woong Lee

Kang-Hee Han

Chang-Lyong Song

In-Jun Yeo

Sun-Joong Song

The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal.

Methods of forming conductive patterns and methods of manufacturing semiconductor devices using the same using an etchant composition that includes phosphoric acid, nitric acid, and an assistant oxidant

Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Methods of manufacturing semiconductor devices

According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.

Non-volatile memory device having vertical structure and method of manufacturing the same

A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

Multiple mold structure methods of manufacturing vertical memory devices

In an etching method, a thin layer is formed on a first surface of a first substrate doped with first impurities having a first doping concentration. The thin layer is doped with second impurities having a second doping concentration lower than the first doping concentration. A second substrate is formed on the thin layer. A second surface of the first substrate is polished. The polished first substrate is cleaned using a cleaning solution including ammonia and deionized water. The cleaned first substrate is etched to expose the thin layer.

Etching methods and methods of manufacturing a CMOS image sensor using the same

A phase changeable memory device is manufactured by forming at least one insulating layer on a substrate. A preliminary first electrode is formed on the insulating layer. The preliminary first electrode is partially etched to form a first electrode electrically connected to the substrate. After the preliminary first electrode is formed, both sidewalls of the preliminary first electrode are partially etched isotropically to form a first electrode having a uniform width and height. A phase changeable material layer pattern and a second electrode are subsequently formed on the first electrode. Related devices also are described.

Methods of manufacturing variable resistance non-volatile memory devices including a uniformly narrow contact layer

A wafer guide for preventing a wafer breakage in a semiconductor cleaning apparatus includes a lower supporter, side supporters, fixing units and stoppers. The lower supporter is provided with a plurality of slots formed with the same interval in a length direction to vertically stand a plurality of wafers thereon. The side supporters are structured and arranged in parallel at each side above the lower supporter. The side supporters support side end parts of the wafers. The fixing units are adapted to support both end parts of the lower supporter and the side supporters, and may be fixed to a bath. The stoppers are individually coupled to each of the fixing units. The stoppers are operable to generate an error in a close operation of holder units of the robot chuck when the robot chuck deviates from a normal alignment range, so as not to perform a wafer chucking, thereby preventing a wafer breakage during the wafer chucking.

Wafer guide for preventing wafer breakage in semiconductor cleaning apparatus

A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride gas on the semiconductor structure.

Methods of forming patterns and capacitors for semiconductor devices using the same

A method of manufacturing a semiconductor device includes forming an insulation pattern over a substrate. The insulation pattern has at least one opening that exposes a surface of the substrate. Then, a first polysilicon layer is formed over the substrates such that the first polysilicon layer fills the opening. The first polysilicon layer also includes a void therein. An upper portion of the first polysilicon layer is removed such that void expands to a recess and the recess is exposed. A second polysilicon layer is formed over the substrate such that the second polysilicon layer fills the recess.

Method of manufacturing a semiconductor device having voids in a polysilicon layer

Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same. An etching solution including hydrogen peroxide (HO) and ammonium hydroxide (NHOH) by a volume ratio of about 1:2 to about 1:10 mixed in water. In a method of forming a pattern and methods of manufacturing a multiple gate oxide layer and a flash memory device, a polysilicon layer may be formed on a substrate. An insulation layer pattern including an opening exposing the polysilicon layer may be formed on the polysilicon layer. The polysilicon layer exposed by the insulation layer pattern may be etched using the etching solution. A polysilicon layer pattern may be formed on the substrate using the etching solution.

Etching solution, method of forming a pattern using the same, method of manufacturing a multiple gate oxide layer using the same and method of manufacturing a flash memory device using the same

Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 &#x212b; to about 200 &#x212b;. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.

Methods of forming non-volatile memory devices having floating gate electrodes

A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.

Etching method for manufacturing semiconductor device

Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.

Method of manufacturing a semiconductor device

Disclosed is an organic stripping composition and a method of etching a semiconductor device in which the generation of an Si pitting phenomenon can be prevented. The composition includes a compound including a hydroxyl ion (OH), a compound including a fluorine ion (F) and a sufficient amount of an oxidizing agent to control the pH of the composition within the range of from about 6.5 to about 8.0. The method includes dry etching an oxide by a dry etching using a plasma, and then ashing the etched oxide using an ashing process to remove an organic material. The method further includes supplying the organic stripping composition to remove residues including any residual organic material, a metal polymer, and an oxide type polymer. The stripping composition is stable onto various metals and does not induce the Si pitting phenomenon.

Organic stripping composition and method of etching oxide using the same

Cleaning solutions for integrated circuit devices and methods of cleaning integrated circuit devices using the same are disclosed. The cleaning solution includes about 30% aqueous ammonia solution, acetic acid by a volume percent higher then a volume percent of the aqueous ammonia solution, and deionized water by a volume percent higher then the volume percent of the acetic acid. Additionally, disclosed are methods wherein the cleaning solution is formed on integrated circuit substrates having an exposed metal pattern formed thereon, and further providing mega-sonic energy to the film of the cleaning solution.

Cleaning solution including aqueous ammonia solution, acetic acid and deionized water for integrated circuit devices and methods of cleaning integrated circuit devices using the same

Growing community of inventors

Suwon-si, South Korea

Byoung-Moon Yoon