Samsung Electronics Co., Ltd.

Byoung-Ju Kim

Hi-Choon Lee

A semiconductor memory device includes a plurality of sub-wordlines, a plurality of sub-wordlines corresponding a redundancy main wordline, a plurality of redundancy memory cells each being coupled to each of the redundancy sub-wordlines, and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline. The number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline. Therefore, when among the sub-wordlines coupled to the main wordline, a sub-wordline to which a normal main memory cell is coupled is addressed, the main wordline selector is enabled to improve a redundancy flexibility and reduce a circuit area.

Semiconductor memory device

A semiconductor memory device, which is capable of adjusting the number of banks from 2N to N and thus increasing product production and repair efficiency, and a method thereof are provided. The semiconductor memory device includes a switching circuit, a control circuit, and a redundant circuit. The switching circuit selectively transmits a first address or a second address in response to a control signal. The control circuit selectively activates 2 banks in response to N&minus; (where N is a natural number) bank selection addresses and the first address or selectively activates 2 banks in response to the N&minus;1 bank selection addresses. The redundant circuit controls repair of the defective normal memory cells. Each of the 2 banks comprises one memory block. Each of the 2 banks comprises 2 memory blocks, each of which is selectively activated in response to the second address. It is preferable that the defective normal memory cells are repaired in an activated bank in response to an output signal of the redundant circuit.

Semiconductor memory device capable of adjusting the number of banks and method for adjusting the number of banks

Internal signals for integrated circuits are generated by a reset circuit that is responsive to an input signal to generate a reset signal pulse a predetermined time after the input signal is activated, and a dynamic inversion circuit that inverts the input signal in the absence of the reset signal pulse and that assumes an inactive state in response to the reset signal pulse, to thereby produce an output pulse that is activated by the input signal and that is deactivated by the reset circuit as a function of the predetermined time. Methods of operating integrated circuits generate a reset signal pulse a predetermined time after an input signal is activated. The input signal is inverted until the reset pulse is generated, to thereby produce an output pulse that is activated by the input signal and that is deactivated by the reset circuit as a function of the predetermined time. Accordingly, circuits and methods for generating internal clock signals for integrated circuits by dynamic inversion and resetting can rapidly generate internal clock signals from external clock signals and can have reduced susceptibility to noise.

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Seoul, South Korea

Byoung-Ju Kim