Skhynix Inc.

Hynix Semiconductor Inc.

Byoung In Joo

Byoung Young Kim

A memory device includes a memory block including a plurality of pages; and a control logic configured to control, when a read command for a selected page among the plurality of pages is received, a read operation on the selected page to be performed using a plurality of read voltages, wherein the plurality of read voltages are determined based on a reference value for the selected page and a read count representing a number of times a read operation of reading data stored in the selected page is performed after a program operation of storing data in the selected page.

Memory device for performing read operation and operating method thereof

Provided herein is a memory device and a method of operating the same. The memory device includes memory cells coupled between a word line and bit lines, a main processor configured to control program-related voltages that are applied to the word line and the bit lines, a page buffer configured to store data sensed based on threshold voltages of the memory cells, a sensing circuit configured to perform a pass/fail check operation of comparing a sensing current corresponding to the sensed data with a reference current, and a sub-processor configured to control the page buffer and the sensing circuit to perform the pass/fail check operation in parallel with control of the program-related voltages while the main processor controls the program-related voltages.

Memory device with sub-processor for parallel control of program voltage and pass/fail check and method of operating the same

Provided herein may be a memory device and a method of operating the memory device. The memory device includes an operation code generator configured to generate a program code and a verify code in response to a program control code and to output an operation code using the program code and the verify code, a verify counter configured to store a count value acquired by counting the number of verify operations that are performed depending on the verify code, a verify determiner configured to compare the count value with a reference value depending on the result of the verify operation and to generate the program control code to change a step voltage for raising a program voltage depending on the comparison result, and a voltage generator configured to generate the program voltage and a verify voltage depending on the operation code.

Memory device and method of operating the memory device including program verify operation with program voltage adjustment

A memory device, of an electronic device, that controls a start of an operation of a sub microcontroller includes a plurality of memory cells. The memory device includes a command interface logic encoding a command received from an outside of the memory device to generate an encoding signal, a multi-microcontroller circuit including a main microcontroller and a sub microcontroller outputting a setting signal for performing an operation on the plurality of memory cells based on the encoding signal, and a read only memory outputting ROM data corresponding to a ROM address output from the multi-microcontroller circuit. The sub microcontroller receives a micro out signal output from the main microcontroller and simultaneously operates with the main microcontroller, during an operation of the main microcontroller.

Memory device and method of operating the same

A semiconductor device includes a first processor configured to process a first code based on a first clock signal; and a second processor, controlled by the first processor, electrically coupled to a memory, and configured to process a second code based on the first clock signal and a second clock signal, wherein the second clock signal has a faster cycle than the first clock signal.

Semiconductor device for improving code processing speed using faster clock signal

There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

Semiconductor memory device and method of operating the same

Semiconductor memory device and method with temperature detection

Disclosed is a method of driving a semiconductor memory device, which programs first page data and second page data in a selected page of a memory cell array, the method including: transmitting a first data buffer control signal to a data buffer so that a data buffer receives the first page data; transmitting a second data buffer control signal to the data buffer so that the data buffer receives the second page data; determining a program option of the first page data; and programming the first page data and the second page data in the selected page, in which the data buffer receives at least some elements of the second page data while the determining of the program option of the first page data is performed.

Semiconductor memory device and method of driving the same

There are provided a semiconductor memory device and an operating method thereof. The method of operating a semiconductor memory device may include receiving an erase and write (E/W) cycle mode select command and an operation command. The method may include selecting one E/W cycle mode information among a plurality of E/W cycle mode information stored according to the E/W cycle mode select command and storing the selected one E/W cycle mode information. The method may include performing a general operation of a memory cell array according to the one E/W cycle mode information stored and the operation command.

Semiconductor memory device and operating method thereof

The invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a first plane and a second plane each including a plurality of memory blocks, a first read and write circuit and a second read and write circuit suitable for sensing and temporarily storing data programmed into the first and second planes, respectively, and a control logic suitable for controlling the first and second read and write circuits to perform a read operation on the first and second planes, respectively, wherein the control logic controls the first and second read and write circuits to set the temporarily stored data as setting data, performs a new read operation to store new data, or maintains the temporarily stored data, depending on whether the first and second planes are in an LSB program state or an MSB program state.

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program pulse applying operation and a verify operation on the memory cell array, a pass/fail check circuit performing a pass/fail check operation on a program operation including the program pulse applying operation and the verify operation, and a control logic controlling the peripheral circuit and the pass/fall check circuit to perform the pass/fail check operation during the program pulse applying operation.

Semiconductor memory device performing program and program verify operation on the memory cell array including pass/fail check on the program operation

The semiconductor device includes a command decoder and a voltage generation circuit. The command decoder may be suitable for decoding external command signals to generate a preparation signal and a voltage control signal. The voltage generation circuit may be suitable for generating a read voltage signal used in a read operation and a program voltage signal used in a program operation in response to the preparation signal. In addition, the voltage generation circuit may terminate generation of the read voltage signal and the program voltage signal in response to the voltage control signal.

Semiconductor devices and reduction of operation times

A nonvolatile memory device includes a control circuit that generates an integrated activation signal based on a read command signal for instructing start of an read operation and a ready/busy signal, and simultaneously generates a voltage control signal and a path control signal in response to the integrated activation signal, a voltage providing circuit that generates voltages used to perform the read operation in response to the voltage control signal, and path control circuits that control electrical path connection to a memory cell array in which the read operation is performed in response to the path control signal.

Nonvolatile memory device and merthod of operating the same

A semiconductor device includes a page buffer configured to read data out of a memory cell array in response to a bias enable signal, and a control logic configured to generate the bias enable signal and a bias precharge signal that are used to control the memory cell array. The control logic activates the bias enable signal and the precharge signal before a ready/busy signal activating a read operation of the memory cell array is enabled.

Semiconductor device, method for operating the same, and semiconductor system including the same

The present disclosure relates to a semiconductor memory device and a method of operation the semiconductor memory device, which sets an encoding value by sequentially defining ranges used for recognizing distribution of memory cells based on a middle range and then performing a read operation in an order from the middle ranges to an outermost range, thereby capable of using infinite ranges for recognizing the distribution of the memory cells without addition of a circuit to an inside of the semiconductor memory device.

Growing community of inventors

Icheon-si, South Korea

Byoung In Joo