Samsung Electronics Co., Ltd.

Korea Hydro Nuclear Power Co., Ltd.

Byoung Il Lee

Tak Hyung Lee

Jun Ho Cha

Ji Mo Gu

Yu Jin Seo

Jun Eon Jin

Dong Seog Eun

Kyung Jun Shin

Hyun Kook Lee

Su Bin Kang

Ji Hye Kim

Hyun Mog Park

Joon Sung Kim

Joong Shik Shin

Kyeong Jin Park

Hoon Moo Choi

Ji Hoon Park

Seong-hun Jeong

Seong-Hun Jeong

Eun Taek Jung

Soyon Kim

Yun Mi Baek

Jeong In Kim

Seo Kon Kang

Jong Ho Woo

Sung Ho Yoo

A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

Semiconductor memory devices and methods for fabricating the same

A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

Three-dimensional semiconductor device having a first main separation structure and a second main separation structure on a lower structure

A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

Vertical-type memory device

A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.

Semiconductor device including separation lines

Three-dimensional semiconductor device having a memory block and separation structures

A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

Semiconductor device including gates

A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each other in the second direction.

Semiconductor device

Semiconductor Device

A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.

A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

Vertical memory device

Poster

Growing community of inventors

Seoul, South Korea

Byoung Il Lee