International Business Machines Corporation

Rutgers, the State University of New Jersey

Sematech, Inc.

Byoung Hun Lee

Ghavam G Shahidi

Effendi Leobandung

Dominic Joseph Schepis

Paul David Agnello

Heemyong Park

Rino Choi

Theodorus E Standaert

Toshiharu Furukawa

Oleg Gluschenkov

Michael Patrick Chudzik

Prashant Majhi

Kisik Choi

Naim Moumen

Anda C Mocuta

Seung-Chul Song

Katsunori Onishi

Bachir Dirahoui

Akihisa Sekiguchi

Paul Daniel Kirsch

Anthony I-Chih Chou

Kristen Scheer

Craig Henry Huffman

Kin Ping Cheung

Tai-chi Su

Sang Ho Bae

Bernd Ernst Eduard Kastenmeier

Dawei Heh

Heemyoung Park

Jong Hoan Sim

Zhibo Zhang

Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.

Dual metal gates using one metal to alter work function of another metal

A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.

CMOS devices with different metals in gate electrodes using spin on low-k material as hard mask

Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.

Methods for measuring capacitance

Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.

Forming gate oxides having multiple thicknesses

A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

An integrated circuit employing CMOS technology employs a process integration that combines a source/drain silicide with a replacement gate process using a triple layer hardmask that is consumed during the course of processing in which a first temporary gate sidewall spacer defines an area for the formation of the raised source and drain and a second temporary spacer defines an area for the implant of the source and drain and for the siliciding of the source and drain while the temporary gate is protected from silicidaiton by the hardmask.

Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors

A method of forming an asymmetric extension MOSFET using a drain side spacer which allows a choice of source and drain sides for each individual MOSFET device and also allows an independent design or tuning of the source and drain extension implant dose as well as its spacing from the gate. A photoresist mask is formed over at least a portion of each drain region, followed by an angled ion implant during which the photoresist mask and the gate conductor shield the nitride layer over at least a portion of the drain region and at least one sidewall of the gate conductor from damage by the angled ion implant which selectively damages portions of the nitride layer unprotected by the photoresist mask and the gate conductor. Then damaged portions of the nitride layer are removed while leaving undamaged portions of the nitride layer as a nitride mask to protect at least a portion of each drain region and at least one gate sidewall from a subsequent dopant implant, which is performed into the source regions and the drain regions while using the undamaged portions of the nitride layer as a mask to form the asymmetric extension MOSFET device. In some embodiments the nitride mask can be etched to form drain side spacers to provide different spacings for the source and drain extension ion implants.

Method of forming asymmetric extension mosfet using a drain side spacer

A dual work function CMOS metal gate device provides a composite metal gate electrode structure. The composite metal gate structure includes a bulk metal and a thin metal layer having an appropriate work function for the transistor type and desired threshold voltage, V . Both N-channel and P-channel transistors are formed to have distinct threshold voltages by incorporating the metal material having the appropriate work function for the desired V into the composite metal gate electrode. The two different electrodes of the N-channel and P-channel transistors are electrically connected by means of the bulk metal.

Integration of dual workfunction metal gate CMOS devices

Growing community of inventors

Wappingers Falls, NY, United States of America

Byoung Hun Lee