Samsung Electronics Co., Ltd.

Byoung Ho Kwon

Chang Sun Hwang

Bo Un Yoon

Chung Ki Min

Hyun Ku Kang

Han Sol Seok

Yong Hee Lee

Kun Tack Lee

Hyo Jung Kim

Ki Chul Park

Ki Hoon Jang

Myung-Ki Hong

Ye Hwan Kim

Young Beom Pyon

A chemical mechanical polishing method is provided. A chemical mechanical polishing method comprising providing a polishing pad, supplying a first purging compound having a first temperature onto the polishing pad, supplying a first slurry having a third temperature onto the polishing pad supplied with the first purging compound, supplying a second purging compound having a second temperature lower than the first temperature onto the polishing pad, and supplying a second slurry having a fourth temperature lower than the third temperature onto the polishing pad supplied with the second purging compound.

Chemical mechanical polishing apparatus, chemical mechanical polishing method and method for fabricating semiconductor device

A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

Method for forming a semiconductor device having protrusion structures on a substrate and a planarized capping insulating layer on the protrusion structures

Semiconductor device with a stacked structure and a capping insulation layer

A method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.

Method of manufacturing a semiconductor device

A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

Semiconductor devices including insulating capping structures

Growing community of inventors

Hwaseong-si, South Korea

Byoung Ho Kwon