Samsung Electronics Co., Ltd.

Byoung-Ho Kim

Weon-Ho Park

Hyun-Khe Yoo

Seung-Beom Yoon

Sung-Chul Park

Ju-Ri Kim

Sang-Soo Kim

Jeong-Uk Han

Kwang-Tae Kim

Jeong-wook Han

Min-Su Kim

Sung-Woo Park

Weon-ho Park

Hyun-khe Yoon

A voltage supply device comprises: a charge pump configured to boost a power voltage and to supply the boosted power voltage to a output line; and a voltage control circuit configured to maintain a voltage level of the output line at a target voltage level; wherein the voltage control circuit comprises a reach-through element including a first region and a second region provided in a well, the reach-through element configured to control the voltage level of the output line, using a reach-through function between the first region and the second region.

Voltage supply device and nonvolatile memory device having the same

A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.

Single chip data processing device with embedded nonvolatile memory and method thereof

Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same

A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.

Method of manufacturing NOR-type mask ROM device and semiconductor device including the same

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Suwon-si, South Korea

Byoung-Ho Kim