Electronics and Telecommunications Research Institute

Byoung-Gue Min

Hyung Sup Yoon

Jong-Won Lim

Seong-Il Kim

Eun Soo Nam

Dong Min Kang

Jae Kyoung Mun

Hae Cheon Kim

Sang-Heung Lee

Hokyun Ahn

Jongmin Lee

Kyu Jun Cho

Jong Min Lee

Ho Kyun Ahn

Dong-Young Kim

Jae Won Do

Sang Choon Ko

Chull Won Ju

Hong Gu Ji

Hyun Wook Jung

Yoo Jin Jang

Woojin Chang

Young Rak Park

Sungjae Chang

Hyunwook Jung

Min Jeong Shin

Sang Heung Lee

Kyung-Ho Lee

Yong-Hwan Kwon

Sung-Bum Bae

Hyung Seok Lee

Seong Il Kim

Jong-Min Lee

Jeong-Jin Kim

Jong Yul Park

Jeong Jin Kim

Chul-Won Ju

Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.

Switch circuit for ultra-high frequency band

Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.

Frequency mixer including non-linear circuit

Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.

Semiconductor device having a drain electrode contacting an epi material inside a through-hole and method of manufacturing the same

Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.

Cascode switch circuit including level shifter

A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.

High electron mobility transistor and fabrication method thereof

Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.

Patch antenna

The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.

High reliability field effect power device and manufacturing method thereof

A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a &#x393;-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the &#x393;-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

Field effect transistor and method of fabricating the same

A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Semiconductor device and method of fabricating the same

A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a '+'-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.

Transistor and method of fabricating the same

A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

Semiconductor device and method of manufacturing the same

Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.

Electronic chip and method of fabricating the same

Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.

Vertical capacitors and methods of forming the same

Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced. The method of manufacturing a field effect type compound semiconductor device includes: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa region in predetermined regions of the first oxide layer, the ohmic layer, and the active layer; planarizing the mesa region after forming a nitride layer by evaporating a nitride on the mesa region; forming an ohmic electrode on the first oxide layer; forming a minute gate resist pattern after forming a second oxide layer on a semiconductor substrate in which the ohmic electrode is formed and forming a minute gate pattern having a under-cut shaped profile by dry-etching the first oxide layer, the nitride layer, and the second oxide layer; forming a gate recess region by forming a head pattern of a gamma gate electrode on the semiconductor substrate; and forming the gamma gate electrode by evaporating refractory metal on the semiconductor substrate in which the gate recess region is formed.

Growing community of inventors

Daejeon, South Korea

Byoung-Gue Min