Globalfoundries Inc.

Byoung-Gi Min

Xusheng Kevin Wu

Ming Lei

Hong Yu

Qi Zhang

Jianwei Peng

Hsien-Ching Lo

Zhao Lun

Ki Young Lee

Tao Han

Wen Zhi Gao

Jeasung Park

Kijik Lee

Basab Banerjee

Hongxiang Mo

A method and apparatus for detecting VC defects and determining the exact shorting locations based on charging dynamics induced by scan direction variation are provided. Embodiments include providing a substrate having at least a partially formed device thereon, the partially formed device having at least a word-line, a share contact, and a bit-line; performing a first EBI on the at least partially formed device in a single direction; classifying defects by ADC based on the first EBI inspection; selecting DOI among the classified defects for further review; performing a second EBI on the DOI in a first, second, third, and fourth direction; comparing a result of the first direction against a result of the second direction and/or a result of the third direction against a result of the fourth direction; and determining a shorting location for each DOI based on the one or more comparisons.

Charge dynamics effect for detection of voltage contrast defect and determination of shorting location

A method and device for characterizing a DC parameter of a SRAM device based on TDCD are provided. Embodiments include forming a SRAM test device, the SRAM test device having a top edge and a bottom edge and at least a first and a second S/D contact, a gate contact, and a channel region; inducing an inversion charge in the channel region through the gate contact; scanning the first S/D contact with an ebeam subsequent to inducing the inversion charge; and characterizing at least one DC parameter of the SRAM test device based on a dissipation of the inversion charge between the steps of inducing and scanning

Device characterization by time dependent charging dynamics

At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a bulbous fin head. A fin of a gate of a transistor is formed. A first recess step is performed for striping a hard mask material by a first dimension to expose a first portion of the fin. An epitaxy layer is formed upon the first portion. An oxidation process is performed upon the fin. An oxide removal process is performed upon the fin to provide a bulbous shape upon the first portion.

Methods, apparatus and system for fabricating high performance finFET device

A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.

Multi-layer spacer used in finFET

Methods of using a nitride to protect source/drain regions during dummy gate removal and the resulting devices are disclosed. Embodiments include forming an oxide layer on a substrate; forming a nitride protection layer on the oxide layer; forming a dummy gate layer on the nitride protection layer; patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate; forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively; growing first and second eSiGe source/drain regions in the first and second source/drain cavities, respectively; and removing the first dummy gate and the second dummy gate stack.

Nitride layer protection between PFET source/drain regions and dummy gate during source/drain etch

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Cohoes, NY, United States of America

Byoung-Gi Min