Samsung Electronics Co., Ltd.

Byongju Kim

Young-Min Ko

Dongsung Choi

Kwangmin Park

Jonguk Kim

Jaeho Jung

Jeong-Hee Park

Jeonghee Park

Jaeyoung Ahn

Jong-Uk Kim

Jumi Yun

Jaemin Jung

Donghwa Lee

Changheon Cheon

A method of manufacturing a semiconductor device is provided including the operations of forming a peripheral circuit structure including a substrate, circuit elements on the substrate, and interconnections on the circuit elements. The method includes forming a plate layer on the peripheral circuit structure, forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on the plate layer in a first direction perpendicular to an upper surface of the plate layer, and patterning the stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers. The method includes forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers, forming selective deposition layers on exposed surfaces of the patterned sacrificial layers, forming channel structures penetrating through the preliminary stack structure in the first direction, and contacting the plate layer.

Methods of manufacturing semiconductor devices

A method of manufacturing a variable resistance memory device may include: forming a memory cell including a variable resistance pattern on a substrate; performing a first process to deposit a first protective layer covering the memory cell; and performing a second process to deposit a second protective layer on the first protective layer. The first process and the second process may use the same source material and the same nitrogen reaction material, and a nitrogen content in the first protective layer may be less than a nitrogen content in the second protective layer.

Variable resistance memory device and method of manufacturing the same

A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.

Variable resistance memory device and method of fabricating the same

A method of manufacturing a variable resistance memory device includes: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulating layer covering a sidewall of the switching element. The forming the sidewall insulating layer includes: a preliminary step of supplying a silicon source to an exposed sidewall of the switching element; and a main step of performing a process cycle a plurality of times, the process cycle comprising supplying the silicon source and supplying a reaction gas, A time duration of the supplying the silicon source in the preliminary step is longer than a time duration of the supplying the silicon gas in the process cycle in the main step.

There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.

Variable resistance memory devices

A semiconductor device has a vertical channel and includes a first tunnel insulating layer adjacent to a blocking insulating layer, a third tunnel insulating layer adjacent to a channel pillar, and a second tunnel insulating layer between the first and third tunnel insulating layers. The energy band gap of the third tunnel insulating layer is smaller than that of the first tunnel insulating layer and is larger than that of the second tunnel insulating layer.

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Hwaseong-si, South Korea

Byongju Kim