Skhynix Inc.

Byong Woo Ryu

Jeong Hyun Kim

Ku Ik Kwon

Ji Hun Choi

Sung Ju Yoo

Kyeong Seok Kim

Yong Joon Joo

Na Young Lee

Son Hong Min

Su Ik Park

Jin Won Jang

Min Su Son

Disclosed are a controller and an operating method thereof. According to an embodiment of the present disclosure, a controller that controls a memory device, comprises: a host interface for determining a remaining resource index and outputting a task scheduling instruction when a data throughput determined based on data inputted/outputted between a host and the controller is lower than a maximum throughput required under a current workload pattern; and a processor for: selecting, in response to the task scheduling instruction, at least one of a plurality of internal tasks based on the remaining resource index and resource consumption indexes of the respective internal tasks, and performing the selected internal task while performing an input/output task.

Controller and method of performing internal operation thereof

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may receive a default enabled information from the host. The default enabled information indicates whether the host maintains a configuration of a host memory buffer in the host and target data stored in the host memory buffer when the memory system is in a low power mode state in which power supplied from the host is cut off.

Memory system and operating method supporting fast boot using host memory buffer and default enabled information

A host device includes a Host Memory Buffer (HMB) including a plurality of memory areas, each memory area configured to store data provided from a storage device which is in communication with the host device, and a host controller configured to generate reliability information of each of the plurality of memory areas, and in communication with the storage device to provide the reliability information to the storage device.

Host device, memory controller, and computing system including the same

The present technology provides a method of operating a host communicating with a memory system including a journal area and a data area. The method of operating the host includes determining to update old data stored in the memory system, transferring, to the memory system, a write command for writing journal data and meta journal data for updating the old data to the journal area, and transferring, to the memory system, a write command for writing new data corresponding to the journal data to the data area in response to a write completion of the meta journal data and the journal data received from the memory system. Each of the meta journal data and the journal data includes a descriptor identifier (ID) indicating the same write transaction.

Method of operating host and memory system connected thereto

Provided herein is a memory controller for controlling a memory device. The memory controller includes a workload detector configured to determine a change in workload based on reception of a changed request from a host or a change in clock received from an external device, a device performance controller configured to determine, if the workload is determined as changed, read performance based on a ratio of a size of data output to the host to a size of data requested from the host every preset period and configured to output a read-look-ahead (RLA) command to the memory device based on the determined read performance, a buffer memory configured to store data read from the memory device in response to the RLA command and a memory size controller configured to control a size of the buffer memory. The RLA command instructs to output data which is frequently requested from the host.

Memory controller and method of operating the same

Embodiments of the present disclosure relate to a storage system and an operating method thereof. According to the embodiments of the present disclosure, the storage system may include N (N is a natural number) temperature sensors and M (M is a natural number of 2 or more) modules, and may determine a thermal throttling level for each of the M modules based on N temperature information pieces collected from the N temperature sensors and N weights corresponding to the N temperature sensors, wherein the N weights are different for each of the M modules, and the storage system may perform the thermal throttling for the M modules based on the thermal throttling levels for the M modules respectively.

Growing community of inventors

Gyeonggi-do, South Korea

Byong Woo Ryu