Samsung Electronics Co., Ltd.

Byong-Kwon Lee

Chul-Sung Park

Hyang-Ja Yang

Yong-Hwan Noh

Young-Dae Lee

Kwang-Jin Lee

Soo-Hwan Kim

Chang-sik Kim

A test circuit of a semiconductor memory device for performing a test in cooperation with a tester having a plurality of input/output pins connected to a plurality of input/output lines. The test circuit may include a first comparing unit adapted to compare, on a bit-by-bit basis, read data that may be read from memory cells corresponding to an address with expected data, and to output the comparison results as first comparison signals, a second comparing unit adapted to perform a logic operation on the first comparison signals and to generate a flag signal when determining a failure of at least one of the memory cells on the basis of the operation result, and a storage unit adapted to store the first comparison signals in response to the flag signal.

Test circuits of semiconductor memory device for multi-chip testing and method for testing multi chips

Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.

Semiconductor integrated circuit device with test element group circuit

An apparatus and method for controlling an input termination of a semiconductor memory device that easily detect and analyze defects, functions and reliability of the device by controlling operations of the input termination. The apparatus comprises an input termination circuit for matching an impedance of a transmission line, a control circuit for processing test commands and outputting control signals in response to said processing, and a switching circuit for selectively turning on/off the input termination circuit in response to the control signals output from the control circuit.

Apparatus for controlling input termination of semiconductor memory device and method for the same

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Suwon-shi, South Korea

Byong-Kwon Lee