Samsung Electro-mechanics Co., Ltd.

Byeung Gyu Chang

Won Hee Yoo

Yong Suk Kim

Taek Jung Lee

Ki Pyo Hong

Min Cheol Park

Sang Jin Kim

Moon Soo Park

Ho Joon Park

Sung Yeol Park

Jeong Ho Yoon

Yun Hwi Park

Dae Hyeong Lee

Byung Taek Kim

Hee Ju Son

Ji Hwan Shin

Gyu Man Hwang

Disclosed herein are a thin film electrode ceramic substrate and a method for manufacturing the same. The thin film electrode ceramic substrate includes: a ceramic substrate; one or more anti-etching metal layers formed in a surface of the ceramic substrate; thin film electrode pattern formed on the anti-etching metal layers; and a plating layer formed on the thin film electrode pattern, wherein respective edge portions of the thin film electrode pattern are contacted with the anti-etching metal layer, and thus, an undercut defect occurring between the surface of the ceramic substrate and the thin film electrode pattern and between the thin film electrode patterns due to an etchant can be prevented and the binding strength of the entire thin film electrode pattern can be enhanced, resulting in securing durability and reliability of the thin film electrode patterns.

Thin film electrode ceramic substrate and method for manufacturing the same

The present invention relates to a method for forming electrode patterns of a ceramic substrate including the steps of: forming a plurality of conductive adhesion patterns on the ceramic substrate to be separated apart from one another; forming a plating seed layer, covering the conductive adhesion patterns, on the ceramic substrate; forming photoresist patterns, exposing parts corresponding to the conductive adhesion patterns, on the plating seed layer; forming a plating layer on the plating seed layer exposed by the photoresist patterns; removing the photoresist patterns; and etching parts of the plating seed layer exposed by removal of the photoresist patterns.

Method for forming electrode pattern of ceramic substrate

Disclosed are a probe substrate and a probe card using the same. The probe substrate includes a ceramic stack structure stacked with a plurality of layers; vias disposed in the ceramic stack structure to perform inner-layer connection, and pads electrically connected to the vias; a contact opening disposed at the ceramic stack structure, and partially exposing the pads; and contact pads disposed at side walls of the contact opening, electrically connected to the pads, and electrically connected to pogo pins.

Probe substrate with auxiliary contact pads and probe card therewith

Provided is a method of manufacturing a ceramic probe card. A ceramic laminated body having a plurality of ceramic green sheets and an interlayer circuit including a conductive via and a conductive line formed in the plurality of ceramic green sheets is prepared. Then, at least one probe pin structure connected to the interlayer circuit is formed by selectively removing the plurality of photosensitive ceramic sheets having a ceramic powder and a photosensitive organic component on the ceramic laminated body necessarily, and by filling a metal material in a region from which the plurality of photosensitive ceramic sheets have been removed. Then, a ceramic substrate having the at least one probe pin structure is provided by simultaneously firing the ceramic laminated body and the photosensitive ceramic sheets, and by removing the photosensitive ceramic sheets.

Method of manufacturing ceramic probe card

Provided is a method of manufacturing a ceramic multi-layer circuit substrate. A plurality of ceramic blocks, in each of which one or more ceramic green sheets having via-electrodes are layered one atop the other, are formed and are then fired. The fired ceramic blocks are aligned with each other. One or more bonding green sheets each having bonding electrodes in positions corresponding to the via-electrodes of the ceramic blocks are prepared. Each of the bonding green sheets is interposed between a pair of the ceramic blocks opposing each other. The ceramic blocks and the bonding green sheets are bonded and are then fired.

Ceramic multi-layer circuit substrate and manufacturing method thereof

There is provided a method of manufacturing a multi-layer ceramic condenser. A method of manufacturing a multi-layer ceramic condenser may include: laminating a plurality of dielectric green sheets having internal electrodes formed thereon to form a laminate; forming through holes in a region of the laminate where an external electrode is to be formed; filling the through holes with conductive paste to form the external electrode; cutting the laminate having the external electrode formed thereon; and firing the cut laminate to form at least one multi-layer ceramic condenser.

Method of manufacturing multi-layer ceramic condenser

There is provided a method of manufacturing a multilayer ceramic substrate, the method including: providing a non-sintered multilayer ceramic substrate having a plurality of low temperature sintering green sheets laminated therein; disposing a hard-to-sinter constraining green sheet on at least one of top and bottom surfaces of the non-sintered multilayer ceramic substrate; sintering the non-sintered multilayer ceramic substrate having the hard-to-sinter constraining layer disposed thereon; immersing the sintered multilayer ceramic substrate into an acidic solution; and activating a contact between the hard-to-sinter constraining layer and the acidic solution such that the hard-to-sinter constraining layer is removed.

Manufacturing method of multi-layer ceramic substrate

Provided herein is a plasma display panel. The plasma display panel comprises a front substrate, a rear substrate opposite to the front substrate and having address electrodes formed thereon, a lattice-shaped partition wall formed between the front substrate and the rear substrate, a phosphor applied to a discharge space partitioned by the partition wall, and a plurality of scanning electrodes and common electrodes formed in intersection regions of the partition wall and extending perpendicular to the front substrate. The plasma display panel has a sufficient aperture ratio, and thus has enhanced light emitting efficiency. The scanning electrodes and the common electrodes formed in the intersection regions of the partition walls have a vertical construction, thereby effectively preventing the phosphor from being damaged by the plasma. Discharge uniformly occurs at the outer periphery of the discharge cell, thereby inducing effective excitation of the phosphor.

Plasma display panel with display electrodes formed in intersecting portions

Disclosed herein is an array type noise reduction filter. The array type noise reduction filter has a plurality of noise reduction filters horizontally arranged within a single chip. A plurality of noise reduction filters each have an inductance portion, a ground portion, and a capacitance portion. The inductance portion is comprised of first and second coils approximately vertically connected in the chip. The ground portion is arranged over or under the inductance portion. The capacitance portion is arranged over or under the ground portion. A second coil of any inductance portion is constructed to be wound in a direction opposite to a second coil of another adjacent inductance portion.

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Gyunggi-do, South Korea

Byeung Gyu Chang