Samsung Electronics Co., Ltd.

ByeongJu Bae

Seung-Heon Lee

Munjun Kim

Jeonghee Park

Eunkee Hong

Jonguk Kim

Mansug Kang

Honggun Kim

Duckhee Lee

A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

Methods of fabricating semiconductor device

A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.

Resistive memory device

Disclosed are variable resistance memory devices and methods of fabricating the same. The variable resistance memory device may include: a plurality of memory cells, each comprising a variable resistance pattern and a switching pattern; a plurality of conductive lines to which the memory cell is connected; a bottom electrode connecting at least one of the conductive lines to the variable resistance pattern; and a spacer pattern formed on the bottom electrode to be in contact with the variable resistance pattern. The spacer pattern includes a dielectric material doped with an impurity.

Variable resistance memory device and method of fabricating the same

In a method of fabricating a semiconductor device, isolation structures are formed in a substrate to define active regions. Conductive structures are formed on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction. An interfacial layer is conformally formed on the substrate in contact with the conductive structures. A first insulation layer is provided on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed.

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Hwaseong-si, South Korea

ByeongJu Bae