Samsung Electronics Co., Ltd.

Seoul National University

Byeongho Kim

Jaehyun Park

Sunjung Lee

Jungho Ahn

Jaewan Choi

Eojin Lee

Wonkyung Jung

Minbok Wi

Jongwook Chung

Yuhwan Ro

Seungwoo Seo

Suk Han Lee

Kyomin Sohn

Shinhaeng Kang

Sungjoo Yoo

Hweesoo Kim

Jaeyoung Heo

Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit. In a first operation mode, the logic circuit writes first data in the plurality of memory banks based on a first command and a first address received from the host, and performs a first processing-in-memory (PIM) operation based on third data received from the host and the first data. In a second operation mode, the logic circuit writes second data in the plurality of memory banks based on the first command and the first address received from the host, and performs a second PIM operation based on fourth data different from the third data received from the host and the second data.

Memory device for processing in memory and operating method of memory device

A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.

Memory devices and electronic devices outputting event data related to occurrences of errors and operating methods of memory devices

A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Method and apparatus with data processing

A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Semiconductor memory device employing processing in memory (PIM) and operation method of the semiconductor memory device

Growing community of inventors

Seoul, South Korea

Byeongho Kim