Samsung Electronics Co., Ltd.

Byeongchan Lee

Jinbum Kim

Sujin Jung

Nam-Kyu Kim

Bonyoung Koo

Choeun Lee

Kwan Heum Lee

Keum Seok Park

Seokhoon Kim

Sungkwan Kang

Sangbom Kang

Yang Xu

Jinyeong Joe

Sunghil Lee

Jungho Yoo

Chul Kyu Kim

Dongsuk Shin

Kang Hun Moon

Hongsik Yoon

Sungwoo Hyun

Sunyoung Lee

Hyun Jung Lee

Gyeom Kim

Sangsu Kim

Dong Chan Suh

Seong Hoon Jeong

Yoonhae Kim

Hyunjae Kang

Myungil Kang

Hanki Lee

Kwanheum Lee

Jaeyoung Park

Kanghun Moon

Chung Geun Koh

Jieon Yoon

A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Semiconductor device including MOS transistor having silicided source/drain region and method of fabricating the same

A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

Semiconductor devices including source/drain regions having multiple epitaxial patterns

A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

Semiconductor devices and methods of fabricating the same

Semiconductor devices including silicide regions and methods of fabricating the same

Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

Semiconductor device and method of fabricating the same

A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.

A semiconductor device includes a first pattern on a first active region, a second pattern on a second active region, and a third pattern on a third active region. The first pattern is spaced from the second pattern by a first interval corresponding to the width of a first recess between the first and second active regions. The second pattern is spaced from the third pattern by a second interval corresponding to the width of a second recess between the second and third active regions. The first, second, and third patterns includes gate patterns, and the first and second recesses include semiconductor material with a conductivity type different from the active regions. The semiconductor material in one recess extends higher than the semiconductor material in the other recess. The first, second, and third patterns have the same width, and the first and second recesses have different depths.

Semiconductor device

Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., &#x3c;111&#x3e; and any other direction) of the semiconductor substrate.

Methods of fabricating a semiconductor device

A semiconductor device may include a fin active region including a lower fin active region surrounded by a device isolation layer and an upper fin active region protruding from a top surface of the device isolation layer, a gate pattern disposed on top and side surfaces of the upper fin active region, and a source/drain region formed in the fin active region located at a side of the gate pattern. The gate pattern extends onto the device isolation region. The source/drain region includes a trench and epitaxial layers that fill the trench. Sidewalls of the trench include first sidewalls and second sidewalls that connect the first sidewalls to a bottom surface of the trench. The bottom surface of the trench is located at a lower level than the top surface of the device isolation layer beneath the gate pattern, and the second sidewalls of the trench have inclined {111} planes.

Semiconductor device having stressor and method of fabricating the same

Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Semiconductor device and method of manufacturing the same

A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

Semiconductor devices and methods of manufacturing the same

Growing community of inventors

Yongin-si, South Korea

Byeongchan Lee