Samsung Electronics Co., Ltd.

Byeong-Yun Nam

Myeong-Cheol Kim

Kyeong-Koo Chi

Tae-hyuk Ahn

Hyoung-Joon Kim

Dong-Chan Kim

Sung-Il Cho

Sang-sup Jeong

Chang-Jin Kang

Beom-jun Jin

Young-Wook Park

Jung-hyeon Lee

Gyung-Jin Min

Cheol-Kyu Lee

Byong-sun Ju

Jong-Kyu Kim

In-Soo Jung

Dong-Chan Lim

Eun-ae Chung

Chang-jin Kang

Seung-Young Son

Kyung-won Park

Sung-Hoon Chung

Won-jong Yoo

Hyoun-woo Kim

Soo-Ik Jang

Kyeong-Koo Ghi

A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench. An interlayer dielectric is formed on the semiconductor substrate and the second device isolation layer. A conductive contact is formed extending through the interlayer dielectric layer and directly contacting at least a portion of both the active region and the extension portion of the active region overlying the second device isolation layer.

Methods of forming semiconductor devices with extended active regions

A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

Methods of forming capacitor electrodes using fluorine and oxygen

Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Methods of forming capacitor structures including L-shaped cavities

Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein that extend opposite the active region. A trench mask having a second plurality of openings therein is then formed by filling the first plurality of openings with electrically insulating plugs and then etching the patterned first electrically insulating layer using the electrically insulating plugs as an etching mask. A plurality of trenches are then formed in the active region by etching the semiconductor substrate using the trench mask as an etching mask. A plurality of insulated gate electrodes are then formed that extend into the plurality of trenches.

Methods of forming field effect transistors having recessed channel regions

Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cland Nare provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cland Nmay be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, Nmay be supplied at a flow rate of from 45&#x2013;65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas

A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

Semiconductor memory device having self-aligned contacts and method of fabricating the same

A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

Method of forming capacitor for semiconductor device

A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

Semiconductor memory device having multi-layered storage node contact plug and method for fabricating the same

The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Methods of fabricating integrated circuit devices providing improved short prevention

There is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant structure having the bit lines and removing the insulating layer on the bit lines and on the first interlayer dielectric film to form insulating spacers only at both side walls of the bit lines, forming a second interlayer dielectric film on the resultant structure having the insulating spacers and forming a fourth opening self-aligned to the insulating spacers to open the surface of the second pad layer, and filling the fourth opening with a conductive material.

Semiconductor memory device having self-aligned contact and fabricating method thereof

The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Integrated circuit devices providing improved short prevention

Semiconductor memory device having multilayered storage node contact plug and method for fabricating the same

A method of manufacturing a self-aligned contact hole. Gate patterns are formed on a semiconductor substrate with an interposing gate insulating layer, and a first insulating pattern for filling a gap between the gate patterns is provided. A portion of the first insulating pattern is etched by self-aligned contact etching to form a first contact hole. A spacer is formed on a side wall of the first contact hole, and a first plug layer of conductive silicon fills the first contact hole. Partial etchback is performed to etch the first plug and gate pattern to a predetermined thickness, such that the top portion of the spacer projects higher than the surface of the first plug and gate pattern. A second plug layer of conductive silicon fills a gap between the projected spacers, and a thickness of the second plug layer at a portion filling the gap between the spacers is greater than that at a portion deposited on the gate pattern. The second plug layer is then etched back to a uniform thickness to expose the sides of the spacer and the first insulating pattern adjacent to the gate pattern, thereby forming a second plug connected to the first plug. A capping protective layer covers and protects the gate pattern while exposing the top surface of the second plug. A second insulating pattern is formed on the capping protective pattern, which has a second contact hole exposing at least the top surface of the second plug.

Growing community of inventors

Suwon, South Korea

Byeong-Yun Nam