Samsung Electronics Co., Ltd.

Byeong-yeon Cho

Tong-suk Kim

Tae-Je Cho

Hee-Seok Lee

Tae-Hun Kim

Yong-hoon Kim

Heung-Kyu Kwon

Hyung-jun Lim

Sung-Yong Park

Jong-Kook Kim

A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area.

Package-on-package (PoP) semiconductor package and electronic system including the same

A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface.

Semiconductor packages having passive elements mounted thereonto

A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.

Package on package structure

An interposer chip may include an insulating substrate, conductive patterns, and a test pattern. The conductive patterns may be formed on the insulating substrate. Further, the conductive patterns may be electrically connected to conductive wires. The test pattern may be connected to the conductive patterns. A test current for testing an electrical connection between the conductive patterns and the conductive wires may flow through the test pattern. Thus, the interposer chip may have the test pattern connected to the conductive patterns, so that the test current may flow to the test pattern through the conductive wires and the conductive patterns. As a result, an electrical connection between the conductive wires and the conductive patterns may be identified based on the test current supplied to the test pattern.

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Suwon-si, South Korea

Byeong-yeon Cho