International Business Machines Corporation

Globalfoundries Inc.

Other

Kabushiki Kaisha Toshiba

Infineon Technologies Ag

Advanced Micro Devices Corporation

Byeong Yeol Kim

Kangguo Cheng

Xiaomeng Chen

Munir D Naeem

Ramachandra Divakaruni

David M Dobuzinsky

Rama Divakaruni

Michael Vincent Aquilino

William L Nicoll

Huilong Zhu

Jack Allan Mandelman

Oleg Gluschenkov

Sivananda K Kanakasabapathy

Geng Wang

Fee Li Lie

Chengwen Pei

Shreesh Narasimha

Jochen C Beintner

Stuart A Sieg

Allen H Gabor

David J Conklin

Ali Khakifirooz

Veeraraghavan S Basker

Carl John Radens

Judson Robert Holt

Reinaldo Ariel Vega

Herbert Lei Ho

Gary Bela Bronner

Rajarao Jammy

Johnathan E Faltermeier

Xinhui Wang

Ying Li

Dan Mihai Mocuta

Yoichi Otani

James Patrick Norum

Akira Sudo

Devendra K Sadana

Effendi Leobandung

Subramanian Srikanteswara Iyer

Ravikumar Ramachandran

Brian Joseph Greene

Joseph Ervin

Ravi Mahendra Todi

David Michael Fried

Hiroyuki Akatsu

Paul David Agnello

Gregory Costrini

Philip L Flaitz

Mihel Seitz

Shwu-Jen Jeng

Mukesh Vijay Khare

Brian L Tessier

Hasan Munir Nayfeh

Hanfei Wang

Carol J Heenan

Yoichi Takegawa

Haining S Yang

Michael Patrick Chudzik

Laertis Economikos

Rolf Weis

Babar Ali Khan

Roger Allen Booth, Jr

Ulrike Gruening

Timothy A Brunner

Larry Alan Nesbit

Rishikesh Krishnan

Augustin J Hong

Heon Lee

Jay William Strane

Sunfei Fang

Daniel J Jaeger

Yong Meng Lee

Xiang Hu

Colin J Brodsky

Deok-kee Kim

Chienfan Yu

Christopher D Sheraw

Gaku Sudo

Gangadhara Swami Mathad

Mahender Kumar

Junedong Lee

Igor V Peidous

Daewon Yang

Rajiv M Ranade

Russell Herbert Arndt

Linda R Black

Woo-Hyeong Lee

Young-Jin Park

Brian S Lee

Donghun Kang

Benjamin Ryan Cipriany

Roger A Booth

Anne C Friedman

Dirk Tobben

Frank D Tamweber, Jr

George Worth

David Mark Dobuzinksy

Garrett W Oakley

Elizabeth Morales

Stephan P Kudelka

Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

Registration mark formation during sidewall image transfer process

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

Structure and method to prevent EPI short between trenches in FinFET eDRAM

Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

A method of forming a semiconductor wafer includes generating a stress topography model of a semiconductor wafer with a plurality of desired structures in a desired layout. The method also includes determining a topography and calculating a compensation pattern based upon the topography, wherein the compensation pattern balances wafer topography. The method also includes patterning a semiconductor front side with the plurality of desired microstructures in the desired layout. The method also includes patterning the semiconductor back side with a compensation block mask corresponding to the compensation pattern.

Wafer stress control and topography compensation

Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

Capacitor strap connection structure and fabrication method

Various embodiments include methods and integrated circuit (IC) structures. In some cases, an IC can include: a substrate; a deep trench within the substrate; a buried oxide (BOX) layer adjacent the deep trench; a first fin structure over the deep trench; a second fin structure over the BOX layer; an ONO layer over the first fin structure; and a gate electrode contacting the ONO layer.

Integrated circuit structure with insulated memory device and related methods

Capacitor strap connections for a memory cell and device structures for making such capacitor strap connections. A deep trench capacitor is formed in a substrate. A collar comprised of an electrical insulator is formed at least partially inside an upper section of a deep trench in which the deep trench capacitor is formed. A portion of the collar is removed to define a notch extending through the collar, and a connection strap is formed in the notch. A fin is formed from a portion of the substrate, and is coupled by the connection strap with an electrode of the deep trench capacitor that is located inside the deep trench.

Capacitor-transistor strap connections for a memory cell

A self-aligned strap structure can be formed by forming trench capacitors and overlying trench top conductive material portions. End portions of fin mask structures overlie portions of the trench top conductive material portions. A dielectric spacer is formed around each end portions of the fin mask structure to cover additional areas of the trench top conductive material portions. An anisotropic etch is performed to recess portions of the trench top conductive material portions that are not covered by the fin mask structures or dielectric spacers. Conductive strap structures that are self-aligned to end portions of semiconductor fins are formed simultaneously with formation of the semiconductor fins. Access fin field effect transistors can be subsequently formed.

Self-aligned laterally extended strap for a dynamic random access memory cell

A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.

Shallow trench isolation structure having a nitride plug

A method including forming a deep trench in a semiconductor-on-insulator substrate including an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, masking only a top surface of the SOI layer and a sidewall of the SOI layer exposed within an upper portion of the deep trench with a dielectric material without masking any surface of the base substrate exposed within a lower portion of the deep trench, and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layer.

Wet bottling process for small diameter deep trench capacitors

A method including forming a buffer layer between a top pad layer and a bottom pad layer all above a deep trench capacitor embedded in a substrate, forming a fin pattern, defined by one or more sidewall spacers, above the top pad layer using a sidewall image transfer technique, transferring the fin pattern into the top pad layer stopping of the buffer layer, and forming a fin in direct contact with a strap by transferring the fin pattern into the buffer layer, into the bottom pad layer, and into the substrate and an inner electrode of the deep trench capacitor, the fin is formed from a portion of the substrate and the strap is formed from a portion of the inner electrode of the deep trench capacitor.

Fabrication of a deep trench memory cell

A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.

Multi-height multi-composition semiconductor fins

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Lagrangeville, NY, United States of America

Byeong Yeol Kim