Lg Display Co., Ltd.

Byeong-Seong So

Youngsung Cho

Hyung-Uk Jang

Young-Sung Cho

Chul Nam

Joungmi Choi

Seungseok Ryoo

Seung-Ho Heo

Chui Nam

Sungwoo Jun

Joung-Mi Choi

Seung-Seok Ryoo

A display device is disclosed. The display device comprises a display panel including an optical area and a normal area in a display area, and an optical electronic device overlapping at least a portion of the optical area. Two or more subpixels and a lower shield metal may be disposed in a non-transmission area between adjacent transmission areas in the optical area. In the non-transmission area of the optical area, the lower shield metal may include at least one opening overlapping all or a portion of a specific transistor among two or more transistors included in each of the two or more subpixels disposed in the non-transmission area in the optical area.

Display device and display panel including two or more subpixels disposed in the non-transmission area of the optical area and display panel having the same

A display device includes subpixels disposed in a display area for displaying an image. Each subpixel includes a light emitting element; a driving transistor for driving the light emitting element; and a transistor whose turn-on or turn-off may be controlled by a gate signal supplied through a gate line. The subpixels includes a subpixel disposed in a specific area in the display area, and such subpixel may include a compensation capacitor formed by overlapping of a gate node of the driving transistor or a connection pattern connected to the gate node of the driving transistor and the gate line. A voltage level of the gate signal supplied through the gate line is changed to a lower voltage level at a timing at which a data voltage or a voltage resulting from changing of the data voltage is applied to the gate node of the driving transistor.

Display device

A display panel of a display device includes a display area including a first optical area overlapping with a first optical electronic device and a normal area located outside of the first optical area, the first optical area includes a plurality of light emitting areas and a plurality of first transmission areas, and the normal area may include a plurality of light emitting areas, a plurality of signal lines may include a first horizontal line including a first optical horizontal line portion disposed in the first optical area, and a non-optical horizontal line portion disposed in the normal area, and a second horizontal line disposed in the normal area without being disposed in the first optical area, a first outer horizontal line portion disposed in an outer area in the first optical area has a greater length per unit area compared to other portions thereof, or a width of all or a portion of the first horizontal line may be smaller than a width of the second horizontal line, thereby compensating for an RC load difference between the horizontal lines.

Display device and display panel

The present disclosure relates to a display apparatus. The display apparatus includes a plurality of light-transmitting areas disposed between the plurality of pixels. The light-transmitting area is formed between structures disposed in the light-emitting area adjacent to the light-transmitting area, and the structure physically disconnects a cathode layer of the light-emitting area and a cathode layer of the light-transmitting area. The cathode layer may be patterned in the light-transmitting area. Accordingly, when patterning is performed with a laser, it is possible to prevent the edge of the cathode layer from being curled in the outer portion of the light-transmitting area. In addition, it is possible to pattern with low energy and solve the damage due to thermal energy of the laser beam by preventing heat conduction to the light-emitting area of the light-emitting device layer. Further, it is possible to improve the reliability by blocking the moisture permeable path.

Display apparatus including a cathode layer disconnecting structure

Embodiments of the present disclosure relate to a display panel and a display device. The display panel comprises a substrate including a first display area and a second display area each having a plurality of sub-pixels, wherein the number of sub-pixels per unit area in the first display area is less than the number of sub-pixels per unit area in the second display area; a transistor layer disposed over the substrate and including a plurality of transistors; a planarization layer over the transistor layer; a light emitting element layer including a common electrode including a plurality of holes in the first display area, disposed over the planarization layer, and including a plurality of light emitting elements; and an antenna comprising a first antenna electrode disposed in the transistor layer and a second antenna electrode disposed over the first antenna electrode, disposed in the first display area and at least a part of which overlaps the plurality of holes. In the present disclosure, the reception rate of the antenna is improved.

Display panel and display device

A display device includes a display panel including a plurality of subpixels and a plurality of signal lines, the display panel defining a display area having a first optical area and a normal area outside of the first optical area, and a non-display area. The first optical area includes a plurality of light emitting areas and a plurality of first transmission areas, and the normal area includes a plurality of light emitting areas. The display panel includes a plurality of first horizontal lines, among the signal lines, disposed through the first optical area. The first horizontal lines include a bypass line connected to subpixels at both boundaries of the first optical area and not connected to other subpixels inside of the first optical area, and a non-bypass line connected to the subpixels at both boundaries of the first optical area and the subpixels inside of the first optical area.

A display device includes: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines; a data driving circuit configured to supply data signals to the plurality of data lines; a gate driving circuit configured to supply gate signals to the plurality of gate lines; and a power supply circuit configured to supply a first body voltage and a second body voltage having a voltage level that is less than the first body voltage to the plurality of pixels, the plurality of pixels being selectively supplied with the first body voltage and the second body voltage.

Display device and driving method for the same

The present disclosure relates to a power supply device including a gate driving circuit configured to supply gate signals to a plurality of gate lines, a first power supply circuit configured to supply a first initialization voltage having a voltage level between a first voltage level and a second voltage level to a plurality of first initialization power lines, the first initialization voltage having the first voltage level in a first period, a third voltage level between the first and second voltage levels in a second period, and the second voltage level in a third period, and a second power supply circuit configured to supply a driving voltage to a plurality of driving power lines among the plurality of power lines, and a display device including the power supply device.

Power supplier circuit and display device including the same

An electroluminescent display device has a plurality of pixels and each pixel includes a driving transistor having a gate connected to a first node, a source connected to a third node, and a drain connected to a fourth node, the driving transistor generating pixel current corresponding to a data voltage when a high-level source voltage is applied to the third node, an internal compensator comprising a first capacitor connected between the first node and a second node, and a second capacitor connected between the second node and an input terminal for the high-level source voltage, the internal compensator controlling a threshold voltage of the driving transistor with reference to a first scan signal, a second scan signal opposite to the first scan signal in phase, a third scan signal lagging the first scan signal in phase, a fourth scan signal leading the first scan signal in phase, and an emission signal, and a light emitting element connected between a fifth node to be connected to the fourth node and an input terminal for a low-level source voltage.

Electroluminescent display device

An electroluminescent display device having a plurality of pixels is disclosed. Each pixel includes a driving transistor having a gate connected to a first node, a source connected to a third node, and a drain connected to a fourth node, to generate pixel current corresponding to a data voltage when a high-level source voltage is applied to the third node, a light emitting element connected between the fourth node and an input terminal for a low-level source voltage, an internal compensator including first and second capacitors, and switching transistors, and a kick-back compensation transistor to apply a DC voltage higher than an initialization voltage to the first node in a kick-back compensation period between an initialization period and a data writing period.

An electroluminescent display device having a plurality of pixels is disclosed. Each pixel includes a driving transistor having a gate connected to a first node, a source connected to a third node, and a drain connected to a fourth node, the driving transistor generating pixel current corresponding to a data voltage when a high-level source voltage is applied to the third node, a light emitting element connected between the fourth node and an input terminal for a low-level source voltage, an internal compensator controlling voltages of the first to fourth nodes in accordance with operations of a plurality of switching transistors in an initialization period, a data writing period and an emission period, and a refresh transistor configured to apply the high-level source voltage to the second node in accordance with a scan signal in a refresh period preceding an initialization period.

Disclosed is a display apparatus with an integrated antenna, in which an antenna and a touch screen are embedded, and the display apparatus comprises a display panel including a touch screen and an antenna electrode, wherein the display panel is divided into a display area and a non-display area surrounding the display area and includes a pixel array part including pixel driving circuits provided in the display area and an electrode array part provided on the pixel array part and including the touch screen and the antenna electrode, the display area includes a pixel including the pixel driving circuit, and a portion of the touch screen is open.

Display apparatus with integrated antenna

Disclosed is a light emitting display apparatus in which two of three scan signals used by a pixel driving circuit provided in one pixel are supplied through two scan lines provided in the pixel and the other remaining signal is supplied through a scan line provided in another pixel adjacent to the pixel.

Light emitting display apparatus

Disclosed is a shift register including stages for sequentially outputting output pulses including carry and scan pulses. Odd-numbered stages supply corresponding scan pulses to odd-numbered gate lines in a sequential manner, and even-numbered stages supply corresponding scan pulses to even-numbered gate lines in a sequential manner. Each stage includes a carry output unit for generating a carry pulse, based on a first discharge voltage and a clock pulse having a low-level voltage equal to the first discharge voltage, and supplying the carry pulse to at least one of upstream and downstream stages, and a scan output unit for generating a scan pulse, based on a second discharge voltage having a higher voltage than the first discharge voltage and the clock pulse, and supplying the scan pulse to a corresponding gate line.

Shift register

Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal.

Growing community of inventors

Paju-si, South Korea

Byeong-Seong So