Hynix Semiconductor Inc.

Byeong Ho Cho

Sung Woo Ko

Dong Sook Chang

Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape.

Overlay vernier key and method for fabricating the same

An exposure apparatus of a semiconductor device may include an exposure light source; an asymmetric adjustment filter for asymmetrically adjusting intensity of a light which passes through the exposure light source; a photomask for passing the light of which intensity is adjusted by the asymmetric adjustment filter; a projection lens for projecting the light passing through the photomask; and a wafer stage for mounting a wafer on which an image is formed by the light from the projection lens.

Exposure apparatus capable of asymmetrically adjusting light intensity

An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.

Growing community of inventors

Icheon-si, South Korea

Byeong Ho Cho