Skhynix Inc.

Hyundai Motor Company

Hynix Semiconductor Inc.

Kia Corporation

Kia Motors Corporation

Medicalip Co., Ltd.

Byeong Cheol Lee

Woongrae Kim

Dong Han Koo

Ji A Lee

Se Won Lee

Sang Il Park

Seok Won Lee

Jong Seok Han

Sang Joon Park

Jae Boum Park

Don Hyun Choi

Byung Ho Yoon

Ki Hoon Nam

Seung Jun Woo

Kyoung Youn Lee

Seung Min Yang

Chul Kee Park

Yun Sik Dho

A semiconductor device including a main word line driver connected to a metal line and configured to transmit a main word line signal to the metal line in order to access at least one of memory cells that are included in a core circuit, the core circuit connected to the metal line and configured to transmit, as a delay main word line signal, the main word line signal that is received through the metal line. The semiconductor device including a test mode control circuit connected to the metal line. The test mode control circuit configured to receive the delay main word line signal through the metal line. The test mode control circuit configured to perform a test mode in which the test mode control circuit drives the metal line in response to the delay main word line signal.

Semiconductor device providing a test mode related to detecting a defect in a metal line

Artificial intelligence robot

Provided are a method and apparatus for displaying a translucent image. An image display apparatus detects a plurality of voxels overlapping in a depth direction in three-dimensional (3D) image data, determines a first combination ratio for two colors based on transparency values of a first voxel and a second voxel, generates a first mixed color by combining a color of the first voxel with a color of the second voxel at the first combination ratio, and displays a mixed color on a screen.

Method and apparatus for displaying translucent image

A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus

An embodiment joint structure for a robot includes an upper plate provided in an upper region, a link part coupled to a lower surface of the upper plate, wherein the link part includes a first link and a second link, and wherein the first link and the second link are provided close to one side of the upper plate with respect to a center of the lower surface of the upper plate, a support part coupled to the lower surface of the upper plate and configured to support the upper plate, wherein the support part is provided to be closer to the center of the lower surface of the upper plate than is the link part, and a motor part configured to provide power to the support part and the link part.

Joint structure for robot and robot including same

A height adjustment module includes a mounting part extending on a plane; a plurality of support arms disposed around the mounting part on the plane on which the mounting part has been extended, and coupled to the mounting part to be rotatable upward or downward; a plurality of travelling parts each being coupled to a first end portion of the support arm, respectively, and including a wheel contacting the ground, respectively; a lift extending over the plane, and connected to second end portions of the plurality of support arms so that vertical movement is interlocked with each other; and a support link coupled to the mounting part to be vertically slidable, and coupled to the lift to be vertically fixed to move the mounting part relative to the lift as the support link is slid in the mounting part.

Height adjustment module and robot system including the same

A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

Semiconductor devices

An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

Address control circuit and semiconductor device including the same

A semiconductor device may be provided. The semiconductor device may include sense-amplifier test device. The sense-amplifier test device may include a drive signal generator configured to generate a test voltage applying signal for supplying a ground voltage to a pull-up power-supply line of a sense-amplifier. The sense-amplifier test device may include a sense-amplifier driver configured to supply a ground voltage to the pull-up power-supply line of the sense-amplifier, based on the test voltage applying signal.

Semiconductor device

A control circuit for a bit-line sense amplifier may include: a bank active signal generator configured to generate an internal active signal and a bank active signal; and a sense amplifier enable signal generator configured to determine a skew in response to the internal active signal, and set an output time of a sense amplifier enable signal by delaying the bank active signal according to the determined skew.

Control circuit for bit-line sense amplifier and semiconductor memory apparatus having the same, and operating method thereof

A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal to control a precharge voltage. The precharge voltage supplying circuit can be widely used in various devices which need the generation of a voltage, a level of which is adjustable according to a PVT characteristic change, and a range of change of which is not so large.

Precharge voltage supplying circuit

The present invention relates to a semiconductor memory device in which current consumption incurred by excessive over-driving can be prevented by dividing a memory core region into a plurality of memory blocks and then over-driving only sense amplifiers of a corresponding memory block.

Growing community of inventors

Seoul, South Korea

Byeong Cheol Lee