Samsung Electronics Co., Ltd.

Byeong Chan Lee

Kwan Heum Lee

Jin Wook Lee

Gyeom Kim

Siyoung Choi

Dong Chan Suh

Yong Hoon Son

Su Jin Jung

Cho Eun Lee

Kwang Yong Yang

Taek Jung Kim

Ji Eon Yoon

Nam Kyu Kim

Jong Ki Jung

In Soo Jung

Deok Hyung Lee

Yoon Hae Kim

Myung Il Kang

Myung Ii Kang

A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations

A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

Semiconductor devices having multiple gate structures and methods of manufacturing such devices

Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.

Multi-structured Si-fin and method of manufacture

Multi-structured Si-fin

Growing community of inventors

Yongin-si, South Korea

Byeong Chan Lee