Samsung Electronics Co., Ltd.

Byeong-Chan Lee

Si-Young Choi

Deok-Hyung Lee

In-Soo Jung

Yong-Hoon Son

Bon-Young Koo

Jin-bum Kim

Su-Jin Jung

Seok-hoon Kim

Chul-Sung Kim

Kwan-heum Lee

Jong-Wook Lee

Jong-Ryeol Yoo

Cho-eun Lee

Woo-bin Song

Seok-Hoon Kim

Nam-Kyu Kim

Seung-Hun Lee

Sang-Bom Kang

Jung-Woo Park

Jong-Ryol Ryu

Jin-Hee Han

Chul Kyu Kim

Young-Pil Kim

Young-pil Kim

Sun-Ghil Lee

Jin-Hwa Heo

Dong-Chan Suh

Jin-yeong Joe

Taek-Jung Kim

Hyun-ho Noh

Kwan-Heum Lee

Heung-Kyu Park

Jae-Hong Kim

Sung-Min Kim

Dong-Won Kim

Pil-Kyu Kang

In-gyu Baek

Hye-Jung Cho

In-Sun Park

Kyoung-hwan Yeo

Sun-ghil Lee

Kwan-Woo Song

Deok-hyung Lee

Kyung-Jae Kim

Young-Eun Lee

Woon-Sik Lee

Tae-Ouk Kwon

Jeong-ho Yoo

Nam Kyu Kim

Yong-Kook Park

In-Deog Bae

Je-Hyeon Lee

Jin-Bum Kim

Soon-Heum Ko

Cho-Eun Lee

Sung-Geun Song

Keum-Seok Park

Jung-Ho Yoo

InSoo Jung

The disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). A method of a server is provided. The method includes determining a target temperature range to be applied to a first zone; predicting an indoor temperature for each of a plurality of zones included in a second zone in which the first zone is included; predicting efficiency of at least one first outdoor unit connected to first indoor units installed at the second zone; and controlling operations of the first indoor units based on the target temperature range, the indoor temperature for each of the plurality of zones, and the efficiency of at least one first outdoor unit.

Apparatus and method for controlling air conditioner in air conditioning system

A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

Semiconductor device with adjacent source/drain regions connected by a semiconductor bridge, and method for fabricating the same

A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

Semiconductor devices having bridge layer and methods of manufacturing the same

Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

Semiconductor devices

A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant.

Semiconductor device and method for fabricating the same

Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices

A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a recess, a plurality of gate structures extending in a second direction crossing the first direction and covering the protruding portions of the active fin structure, a first epitaxial pattern in a lower portion of the recess between the gate structures, a second epitaxial pattern on a portion of the first epitaxial pattern, the second epitaxial pattern contacting a sidewall of the recess, and a third epitaxial pattern on the first and second epitaxial patterns, the third epitaxial pattern filling the recess. The first epitaxial pattern includes a first impurity region having a first doping concentration, the second epitaxial pattern includes a second impurity region having a second doping concentration lower than the a first doping concentration, and the third epitaxial pattern includes a third impurity region having a third doping concentration higher than the second doping concentration. The semiconductor device may have good electrical characteristics.

Semiconductor devices including a finFET

FinFET with a single contact to multiple fins bridged together to form a source/drain region of the transistor

Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

Semiconductor devices having composite spacers containing different dielectric materials

A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.

Method for fabricating semiconductor device

Growing community of inventors

Gyeonggi-do, South Korea

Byeong-Chan Lee