Samsung Electronics Co., Ltd.

Byeng-Soon Choi

Young-Ho Lim

Cheol-Ung Jang

A semiconductor read-only memory includes a main memory cell array having a plurality of first and second bit lines arranged in a hierarchical configuration. A dummy cell array generates a reference potential during a read-out operation. A decoder circuit generates a first, second, third and fourth selection signals from address signals, and a sense amplifier circuit detects data stored in a memory cell of the main memory cell array. A switching circuit connects the dummy cell to the sense amplifier circuit through the second bit line. The read-only memory according to the invention has an advantage that it is possible to accomplish an efficient read-out operation without additional dummy bit lines in an area of the memory cell array.

Semiconductor read-only memory with selection circuitry for routing

An apparatus for controlling reading of memory cells in a memory device includes a word line voltage generator operative to apply a word line voltage to a selected memory cell of memory device responsive to a sensing period signal. A dummy memory cell is coupled to the word line voltage generator such that the word line voltage is applied to the dummy memory cell, the dummy memory cell having a threshold voltage. A sensing period controller is coupled to the dummy memory cell and operative to produce the sensing period signal responsive to a current generated in the dummy memory cell. According to an embodiment of the present invention, the sensing period controller includes a dummy sense amplifier coupled to the dummy memory cell and operative to produce a dummy cell sense amplifier output signal responsive to a current in the dummy memory cell. A sensing time detector is coupled to the dummy sense amplifier and operative to produce a sensing time signal in response to a transition of the dummy cell sense amplifier output signal. A sensing period signal generator is coupled to the sensing time detector and operative to generate the sensing period signal responsive to the sensing time signal. Apparatus for controlling sensing periods in a multi-level memory device, as well as related operating methods, are also described.

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Suwon, South Korea

Byeng-Soon Choi