International Business Machines Corporation

S&c Electric Company

Burton L Oliver

Raymond E Losinger

Joseph P Buonomo

Daniel James Sucher

David C Preston

A multi-microprocessor implemented data processing system having a single cycle data transfer capability for its memory mapped peripheral devices is described. A host or controlling microprocessor provides address and control signals for memory accesses. In addition, it also determines that a peripheral operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means are provided to detect the special decode and to intercept the data bus at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral to enable the desired data transfer after the data bus has been intercepted.

Apparatus and method for direct memory to peripheral and peripheral to

Bus command generation apparatus is provided for a microprocessor implemented data processing system that uses a multibyte width system bus requiring a bus command byte since a complete bus command byte is ordinarily unavailable directly from a microprocessor. A bus command register is loaded with a preliminary bus command, certain bits of which are then modified in accordance with the operation to be performed. The limited command information available from the microprocessor that controls I/O operations is utilized to modify the preliminary bus command bytes without any need to access memory for bus command information. The bus command generation apparatus is adapted to pass a preliminary bus command byte unaltered, under predefined conditions, to the system bus.

Apparatus for expediting sub-unit and memory communications in a

Synchronization of peripheral operation with that of a processor in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. A logic circuit is provided for monitoring the condition of a peripheral's status bits and for preventing an appropriate processor control signal from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest is readily identified by providing unique memory mapped locations, one for each system peripheral, that are responsively connected to the logic circuit.

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Nanticoke, NY, United States of America

Burton L Oliver