Microsoft Technology Licensing, LLC

Cray Incorporated

The Invention Science Fund I LLC

Intel Corporation

Northrop Grumman Systems Corporation

Elwha LLC

University of Notre Dame Du Lac

Burton Jordan Smith

Gail A Alverson

James Robert Hamilton

Lowell L Wood, Jr

Roderick A Hyde

Clarence T Tegreene

Jordin T Kare

Nathan P Myhrvold

Craig J Mundie

Charles David Callahan, Ii

Brian D Koblenz

Edward K Y Jung

Robert W Lord

Charles Whitmer

William Henry Mangione-Smith

Howard Lee Davidson

Robert Victor Welland

Richard F Rashid

Arne M Josefsberg

Michael J Manos

Kenneth Lustig

Jan Stephen Gray

Allan Porterfield

Simon H Kahan

Susan L Coatney

Richard D Korry

Ali-Reza Adl-Tabatabai

Gad Shlomo Sheaffer

Timothy Lawrence Harris

James R Larus

Bratin Saha

David S Callahan

David B Wecker

Laurence S Kaplan

Mark L Niehaus

David Bazeley Tuckerman

Douglas Christopher Burger

Muriel Y Ishikawa

Victoria Y H Wood

Thomas A Weaver

William Henry Gates, Iii

Andrew F Glew

Chris Demetrios Karkanias

Karin Strauss

Michael Richard Fortin

Martin Taillefer

Robert L Alverson

Robert Geva

Darek Josip Mihocka

Douglas M Carmean

John L Manferdelli

Vadim Bassin

David Bradley Probert, Jr

Thomas M McWilliams

Andrew Steven Kopser

Abhishek Kumar Singh

David Tennyson Harper, Iii

David T Harper

Matthias Troyer

Mike Neil

Peter M Kogge

Stuart M Bowers

Kathryn S Mckinley

Richard Thomas Witek

Heather E Warncke

David Callahn

Bryan Clark

Graefe Goetz

Jay B Brockman

Timothy L Harris

Methods and apparatus are disclosed for cooling superconducting signal lines disposed on an interconnect such as a flexible cable or a rigid substrate. The superconducting signal lines are cooled to a cryogenic temperature lower than the temperature at which at least some superconducting logic devices coupled to the interconnect are operated. In some examples, an airtight conduit, heat pipe, or thermally conduct of strap provided to cool the superconducting interconnect. In one example of the disclosed technology, a system includes at least two sets of superconducting logic devices, cooling apparatus adapted to cool the logic devices to a first operating temperature, and interconnect coupling the superconducting logic devices, and a cooling apparatus in thermal communication with the interconnect. The apparatus is adapted to cool superconducting signal lines on the interconnect to a lower operating temperature than the first operating temperature at which the superconducting logic devices operate.

Reducing losses in superconducting cables

A processor having an instruction cache for storing a plurality of instructions is provided. The processor further includes annotation logic configured to determine a lookahead distance associated with an instruction and annotate the at least one instruction cache with the lookahead distance. The lookahead distance may correspond to a number of instructions that separates an instruction that references a register from the most recent register definition. The lookahead distance may indicate the shortest distance to a later instruction that references a register that this instruction defines.

Annotation logic for dynamic instruction lookahead distance determination

A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Non-contacting inductive interconnects

One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic operations on a data sequence received at the input node. The system also includes a scan path connected to the input node and comprising at least one delay element configured to propagate the data sequence from the input to a scan path output to capture values of the data sequence provided to the wave-pipelined combinational logic circuit as a serial data stream. The system also includes a scan point device configured to deliver one of input data and scan data as the data sequence to the wave-pipelined combinational logic circuit and to the scan path via the input node in a respective one of a normal operating mode and a scan mode.

Wave-pipelined logic circuit scanning system

A system for optimizing cache coherence message traffic volume is disclosed. The system includes a plurality of caches in a multi-level memory hierarchy and a plurality of agents. Each agent is associated with a cache. The system includes one or more monitoring engines. Each agent in the plurality of agents is associated with a monitoring engine. The agents can execute a processor level software instruction causing a memory region to be private to the agent. Each of the agents is configured to execute a memory access for data on an associated cache and to send a request for data up the hierarchy on a cache miss. The monitoring engine is configured to intercept request for data from an agent and to prevent snooping for the cache line in peer caches when the cache line associated with a memory region represented as private to the agent.

Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy

A data center for executing a data processing application includes processing units, sub-units or servers. Each of the processing units, sub-units or servers can execute a part or all of the data processing application. The processing units, sub-units or servers are electrical disjoint with respect to data communications, but can communicate with each other over free space optical links.

Data center with free-space optical communications

Operators such as unitary operators common in quantum mechanical applications may be approximated by a Trotter-like approximation. An operator may be decomposed and terms of the operator may be grouped, or assigned into levels. The levels may be scaled and applied at unique intervals of calculational steps. A quantum device may have circuitry for applying levels of the operator at the unique intervals.

Optimized trotterization via multi-resolution analysis

A method and apparatus for accelerating a Software Transactional Memory (STM) system is herein described. A data object and metadata for the data object may each be associated with a filter, such as a hardware monitor or ephemerally held filter information. The filter is in a first, default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access to the metadata, such as a first read, access barrier operations, such as logging of the metadata; setting a read monitor; or updating ephemeral filter information with an ephemeral/buffered store operation, are performed. Upon a subsequent/redundant access to the metadata, such as a second read, access barrier operations are elided to accelerate the subsequent access based on the filter being set to the second state to indicate a previous access occurred. Additionally, mapping of data objects to ephemeral information may be provided by software, such as through a pointer to the ephemeral information associated with the data object; an offset from a base address of the data object to the ephemeral information included associated with the data object; an index into a segment containing the ephemeral information associated with the data object; mapping the data object to the ephemeral information utilizing address arithmetic; and a hash that maps the data object to ephemeral information.

Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata

The techniques discussed herein identify failed segments of memory in a memory region. The techniques may then manage the failed segments of memory by logically clustering the failed segments of memory at an outlying portion of the memory region using a remapping process. The remapping process may include creating and storing remapping metadata defining segment remapping entries for the memory region. Accordingly, the failure clustering logically eliminates or reduces the memory fragmentation so that a system can allocate larger portions of contiguous memory for object storage.

Memory segment remapping to address fragmentation

Various technologies and techniques are disclosed for providing a hardware accelerated software transactional memory application. The software transactional memory application has access to metadata in a cache of a central processing unit that can be used to improve the operation of the STM system. For example, open read barrier filtering is provided that uses an opened-for-read bit that is contained in the metadata to avoid redundant open read processing. Similarly, redundant read log validation can be avoided using the metadata. For example, upon entering commit processing for a particular transaction, a get-evictions instruction in an instruction set architecture of the central processing unit is invoked. A retry operation can be optimized using the metadata. The particular transaction is aborted at a current point and put to sleep. The corresponding cache line metadata in the metadata are marked appropriately to efficiently detect a write by another CPU.

Cache metadata for accelerating software transactional memory

Various technologies and techniques are disclosed for providing a bounded transactional memory application that accesses cache metadata in a cache of a central processing unit. When performing a transactional read from the bounded transactional memory application, a cache line metadata transaction-read bit is set. When performing a transactional write from the bounded transactional memory application, a cache line metadata transaction-write bit is set and a conditional store is performed. At commit time, if any lines marked with the transaction-read bit or the transaction-write bit were evicted or invalidated, all speculatively written lines are discarded. The application can also interrogate a cache line metadata eviction summary to determine whether a transaction is doomed and then take an appropriate action.

Cache metadata for implementing bounded transactional memory

Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts for declaring one or more memory regions private to a particular agent or shared read only amongst agents by having software utilize processor level instructions to specify to hardware the private or shared read only memory address regions. The method includes an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents. As a result of an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents, a hardware component monitoring the one or more memory regions for conflicting accesses or prevents conflicting accesses on the one or more memory regions.

Private memory regions and coherence optimizations

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Seattle, WA, United States of America

Burton Jordan Smith