Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Burn Jeng Lin

Shy-Jay Lin

Wen-Chuan Wang

Jaw-Jung Shin

Pei-Yi Liu

Ching-Yu Chang

Tsai-Sheng Gau

Cheng-Hung Chen

Ru-Gun Liu

Chin-Hsiang Lin

Jyuh-Fuh Lin

Chun-Kuang Chen

Hua-Tai Lin

Chung-Hsing Chang

Jeng-Horng Chen

Ken-Hsien Hsieh

Ya-Chin King

Chrong Jung Lin

Chang-Ming Dai

Jan-Wen You

Chen-Hua Douglas Yu

Hsin-Chang Lee

Ming-Feng Shieh

Wen-Chun Huang

Chien-Wei Wang

Ya Hui Chang

Hsien-Cheng Wang

Tsong-Hua Ou

David Lu

Shih-Chi Wang

Shi-Jiun Wang

Jen Chieh Shih

Tien-I Bao

Anthony Yen

Shinn-Sheng Yu

Chih Wei Lu

Hui-Min Huang

Sheng-Chi Chin

Heng-Jen Lee

Fu-Jye Liang

Tsung-Chih Chien

Tsai Sheng Gau

Shinn Sheng Yu

Chih-Ming Lai

Chi-Wen Liu

Yu-Der Chih

Dian-Hau Chen

Chia-Jen Chen

Chien-Hung Lin

Chih-Ming Ke

Chia-Hui Lin

Chii-Ping Chen

Ming-Hui Chih

Yao-Ching Ku

Ko-Bin Kao

Jen-Chieh Shih

Hung Chang Hsieh

Bang-Ching Ho

Chih-Cheng Chin

May-Be Chen

King-Chang Shu

Lin-Hung Shiu

Ming-Jiun Yao

Ping Yang

Bang Chein Ho

Chun-Kung Chen

Shing Shen Yu

Shing-Sheng Yu

Hong Chang Hsieh

Yao Ching Ku

Chin Hsian Lin

Chiu Shan Yoo

Shou Yen Chou

Jaw Jung Shin

Shih-Ying Chen

Bo Yu Lin

Shy-Jay Shin

Jeng Horng Chen

Wen Chuan Wang

Tsai-Shen Gau

H J Lee

A semiconductor fabrication apparatus and a method of using the same are disclosed. In one aspect, the apparatus includes a holder configured to place a substrate and a radiation source configured to provide radiation to transfer a pattern onto the substrate. The apparatus also includes a plurality of sensing devices configured to provide a reference signal based on an intensity of the radiation when the substrate is not present. The apparatus further includes a controller, operatively coupled to the plurality of sensing devices, configured to adjust the intensity of the radiation based on the reference signal.

Semiconductor fabrication apparatus and method of using the same

A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.

Semiconductor device, manufacturing method thereof, and detecting method using the same

A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

Semiconductor detector

A device includes a semiconductor fin, an isolation structure, a gate structure, source/drain structures, a sensing contact, a sensing pad structure, and a reading contact. The semiconductor fin includes a channel region and source/drain regions on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is over the channel region of the semiconductor fin. The source/drain structures are respectively over the source/drain regions of the semiconductor fin. The sensing contact is directly on the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The reading contact is directly on the isolation structure and adjacent to the gate structure.

Detection using semiconductor detector

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio rto optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Method of fabricating an integrated circuit with non-printable dummy features

Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.

Immersion lithography system using a sealed wafer bath

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity

A processing chamber is disclosed for planarizing material layers (for example, polymer layers). An exemplary processing chamber includes a substrate table configured to support a substrate having a material layer formed thereover and a flattening structure having a substantially flat surface. The flattening structure moves freely with respect to a non-uniform surface of the material layer, such that the non-uniform surface is flattened as the substantially flat surface contacts the non-uniform surface. In some implementations, the processing chamber further includes a pressing mechanism operatively coupled to the flattening structure, and a pivotal interface coupling the flattening structure to the pressing mechanism. The pressing mechanism presses the substantially flat surface of the flattening structure to the non-uniform surface of the material layer, and the pivotal interface allows the flattening structure to pivot with respect to the pressing mechanism and with respect to the substrate.

Method and apparatus for planarizing material layers

A charged particle multi-beam lithography system includes an illumination sub-system that is configured to generate a charged particle beam; and multiple plates with a first aperture through the plates. The plates and the first aperture are configured to form a charged particle doublet. The system further includes a blanker having a second aperture whose footprint is smaller than that of the first aperture. The charged particle doublet is configured to demagnify a portion of the charged particle beam passing through the first aperture, thereby producing a demagnified beamlet. The blanker is configured to receive the demagnified beamlet from the charged particle doublet, and is further configured to conditionally allow the demagnified beamlet to travel along a desired path.

Apparatus for charged particle lithography system

The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.

Systems and methods for high-throughput and small-footprint scanning exposure for lithography

Growing community of inventors

Hsinchu, Taiwan

Burn Jeng Lin