International Business Machines Corporation

Globalfoundries Inc.

Burkhard Steinmacher-Burow

Philip Heidelberger

Dong Chen

Alan G Gara

Noel A Eisley

Robert Matthew Senger

Yutaka Sugawara

Martin Ohmacht

Valentina Salapura

Mark Edwin Giampapa

Sameer Kumar

Paul William Coteus

Todd Edward Takken

Matthias Augustin Blumrich

Joseph D Ratterman

Robert William Wisniewski

Thomas M Gooding

Pavlos Michael Vranas

Krishnan Sugavanam

David L Satterfield

Gabor J Dozsa

Gerard Vincent Kopcsay

Jeffrey John Parker

Rudolf Adriaan Haring

Michael K Gschwind

Michael A Blocksome

James Allan Kahle

Adam James Muff

Bruce Martin Fleischer

Alexandre E Eichenberger

John A Gunnels

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

James Anthony Marcella

Todd Alan Inglett

George L Chiu

Jon K Kriegel

Markus Buehler

Douglas R Miller

Craig Brian Stunkel

Amith R Mamidala

Kristan D Davis

Jose R Brunheroto

Fabrizio Petrini

Michael B Mundy

Matthew Roger Ellavsky

Robert E Walkup

Samuel J Miller

James Lee Van Oosten

Ruth Janine Poole

Thomas A Liebsch

Peter Boyle

Brant L Knudson

Arni Ingimundarson

Ralph E Bellofatto

Norman Christ

Kahn C Evans

Thilo Maurer

William Maupin Stockdell

Alfred Thomas Watson, Iii

Brian E Smith

Dong Chen Chen

Harald Huels

Xiaotong Zhuang

Don Darrell Reed

Luis H Ceze

Ralph A Bellofatto

Phlip Heidelberger

Benedikt Rombach

Alana Gara

Philp Heidelberger

Configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system is disclosed. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. In response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.

Server recovery from a change in storage control chip

A method comprises configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system. Each of the plurality of CPU chips is coupled to each of the SC chips in a leaf-spine topology. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. The method further comprises, in response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.

A computer-implemented method comprises receiving an index number for each of a plurality of physical processing units, each of the plurality of physical processing units communicatively coupled to each of a plurality of switch chips in a leaf-spine topology; assigning at least one of the plurality of physical processing units to a first virtual drawer by updating an entry in a virtual drawer table indicating an association between the respective index number of the at least one physical processing unit and an index of the first virtual drawer; and performing a drawer management function based on the virtual drawer table.

Virtual drawers in a server

Aspects of the disclosure relate to a processor core including an execution unit and a usage ratio controller. The execution unit is operable for executing a command forwarded to the execution unit. The usage ratio controller is operatively coupled with the execution unit. The usage ratio controller is operable for controlling a usage ratio of the execution unit. The usage ratio corresponds to the fraction of an observation time during which the execution unit is executing commands of an application. Other aspects of the disclosure relate to a method for detecting or analyzing a bottleneck in a processor core for a given application. The method includes controlling a usage ratio of at least one execution unit of the processor core and measuring the resulting application performance.

Partial computer processor core shutoff

The invention relates to a method for coordinating an execution of an instruction sequence by a processor device of a coherent shared memory system. An instruction is executed and causes the processor device to fill a copy of a memory line to a processor cache memory. The memory line is flagged by the processor device upon detection of first flag information which indicates that propagation of memory coherence across the shared memory system in respect of the memory line is unconfirmed. The memory line is unflagged by the processor device upon detection of second flag information which indicates that the propagation of memory coherence in respect of the memory line is confirmed. Upon execution of a memory barrier instruction, a completion of execution of the memory barrier instruction is prevented while the memory line is flagged.

Coordination of cache memory operations

A cache memory control device for controlling a first cache memory of a multi-cache memory system that includes logic circuitry operable for storing state information assigned to an invalid copy of a cache line stored in the first cache memory, where the state information includes a cache memory identifier identifying an individual second cache memory of the multi-cache memory system that is likely to contain a valid copy of the cache line.

Cache line states identifying memory cache

Computer-implemented methods for accessing a particular element of a plurality of elements stored in an N-way linked list in a computer memory provide for adding or removing elements at locations within the list. The methods may be employed with LIFO or FIFO N-way linked lists. The methods may include traversing the N sub-lists in parallel as well as the use of single instruction multiple data operations.

Accessing an N-way linked list

A buffer is configured to store a plurality of last addresses accessed by a processor core from a memory. A minimum distance extraction circuit determines distances of a current memory address accessed by the processor core from each of the plurality of last addresses in the buffer and determines a minimum distance from the distances. A limit determination circuit compares the minimum distance to each of a plurality of ranges of distances and selects a range of the plurality of ranges within which the minimum distance falls. Each of a plurality of counters of a counter circuit is associated with a corresponding one of the plurality of ranges. A counter of the plurality of counters is to be incremented corresponding to the selected range.

Hardware apparatus to measure memory locality

A first method includes determining a total length of pending packets for a network link, determining a currently preferred power mode for the network link based on the total length of pending packets for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein. A second method includes determining a utilization for a network link, determining a currently preferred power mode for the network link based on the utilization for the network link, and changing a current power mode for the network link to the currently preferred power mode. A corresponding apparatus is also disclosed herein.

Power management of network links

A shared memory maintained by sender processes stores a sequence number counter per destination process. A sender process increments the sequence number counter in the shared memory in sending a message to a destination process. The sender process sends a data packet comprising the message and at least a sequence number specified by the sequence number counter. All of the sender processes share a sequence number counter per destination process, each of the sender processes incrementing the sequence number counter in sending a respective message. Receiver processes run on the hardware processor, each of the receiver processes maintaining a local memory counter on the memory, the local memory counter associated with a sending node. The local memory counter stores a sequence number of a message received from the sending node. The receiver process delivers incoming data packets ordered by sequence numbers of the data packets.

Reduced number of counters for reliable messaging

Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.

Embedding global barrier and collective in a torus network

A computer implemented method for managing cache requests includes creating a transient table including records corresponding to one or more participant caches in a system, receiving a new request with respect to an address, wherein the request includes one or more controller actions to be executed, and wherein the request corresponds to one of the one or more participant caches in the system, determining whether an entry exists in the directory table corresponding to the address indicated by the received request, determining whether an entry exists in the transient table for the address indicated by the received request, processing the transient entry indicated by the index in the directory entry to provide a current state of the address indicated by the received request, and appropriating requested controller actions according to the directory table entry, the transient entry, and the received request.

Non-blocking directory-based cache coherence

An injection descriptor corresponding to a destination node may be stored in memory. A network interface controller (NIC) may determine that one or more messages added to the injection descriptor are to be transmitted to the destination node. The NIC may then lock the injection descriptor so that no additional message can be added to the injection descriptor, and the NIC may load the one or more messages. The NIC may then generate a network packet that includes the one or more messages, and the NIC may transmit the network packet to the destination node.

Coalescing messages using a network interface controller

Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips and a methodology for operating the computer system. The memory buffer chips may be communicatively coupled to at least one memory module which can be configured for storing memory lines and assigned to the memory buffer chip. The processor chips can include a cache configured for caching memory lines. The processor chips may be communicatively coupled to the memory buffer chips via a memory-buffer-chip-specific bidirectional serial point-to-point communication connection. The processor chips can be configured for transferring memory lines between the cache of the processor chip and the memory modules via the respective memory-buffer-chip-specific bidirectional serial point-to-point communication connection.

Uniform memory access architecture

Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips, and for transferring data in the computer system. One or more of the processor chips is communicatively coupled to at least one memory module which is assigned to the processor chip. One or more of the processor chips includes a cache and is communicatively coupled to one or more of the memory buffer chips via a memory-buffer-chip-specific bidirectional point-to-point communication connection. At least one of the memory buffer chips includes a coherence directory and is configured for being exclusively in charge for implementing directory-based coherence over the caches of the processor chips for at least one pre-defined address-based subset of memory lines stored in at least one of the memory modules assigned to a processor chip.

Memory access architecture with coherence

Growing community of inventors

Esslingen, Germany

Burkhard Steinmacher-Burow