United States of America as Represented by the Secretary of the Air Force

Anadigics, Inc.

Burhan Bayraktaroglu

Kevin D Leedy

Chern I Huang

Lee L Liou

A method of fabricating a multi-zone, short gate length thin film transistor is provided. Gate metal and a plurality of layers are deposited on a substrate. The layers include a gate insulator, a first semiconductor, a second semiconductor, and source contact metal. An insulator is deposited on the plurality of layers partially overlapping the gate electrode and masking part of the plurality of layers. Portions of the source contact metal not masked by the insulator are removed and the first and second semiconductors are diffused with dopants via a plasma. Sidewalls of the insulator and source metal contact are covered with an insulating layer. Portions of the second semiconductor not masked are removed by etching for a length of time to create undercuts below the insulator and extending under the source contact metal. The undercuts are filled with an insulating material and an external metal contact layer is deposited.

Fabrication method for multi-zoned and short channel thin film transistors

A method is provided for fabricating an ultra short gate length thin film transistor. A plurality of layers is deposited on a substrate including a refractory metal and a first and second photosensitive material. The second material is sensitive to longer wavelength optical radiation than the first material and the first material is not soluble in chemicals used to develop or strip the second material. A source contact pattern is defined in the second material to mask the first photosensitive material. The first material is processed to produce an undercut of the first material with respect to the second material. A metal layer is deposited at a normal incidence on the second material and an exposed portion of the refractory metal. The second material is removed. Exposed portions of the refractory metal corresponding to the undercut of the first material are removed to form a gap in the refractory metal.

Method of fabricating ultra short gate length thin film transistors using optical lithography

A method is provided for fabricating a thin film transistor. An insulating and a metal gate contact layer are deposited on a substrate with the insulating layer being positioned between the gate contact layer and the substrate. A portion of the gate contact layer is selectively removed utilizing reactive ion etching incorporating a gas that etches the gate contact layer but not the insulating layer. A plurality of layers is deposited over a remaining portion of the gate contact layer and insulating layer, which include a gate insulating layer, a channel layer, and a metal film. A portion of the metal film is selectively removed utilizing reactive ion etching incorporating the gas that etches the metal film but not the channel layer. The insulating layer includes a high resistivity insulator that can be deposited at temperatures less than 400&#xb0; C. and the channel layer is comprised of a metal oxide semiconductor.

Metal oxide thin film transistor fabrication method

A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor.

Fabrication method for ZnO thin film transistors using etch-stop layer

A thermal and electrical interconnect for heterojunction bipolar transistors is disclosed wherein the interconnect is essentially comprised of gold and in thermal and electrical contact with each of the interdigitated emitter fingers and is capable of transporting heat fluxes between 0.25-1.5 mW/&mgr;m2. The interconnect is electrodeposited to form a low-stress interface with the emitter finger, thereby increasing the lifetime and reliability of the transistor.

Low stress thermal and electrical interconnects for heterojunction bipolar transistors

Structure and fabrication details are disclosed for AlGaAs/GaAs microwave HBTs having improved thermal stability during high power operation. The use of a thermal shunt joining emitter contacts of a multi-emitter HBT is shown to improve this thermal stability and eliminate 'current-crush' effects. A significant reduction in thermal resistance of the disclosed devices is also achieved by spreading the generated heat over a large substrate area using thermal lens techniques in the thermal shunt. These improvements achieve thermally stable operation of AlGaAs/GaAs HBTs up to their electronic limitations. A power density of 10 mW/.mu.m2 of emitter area is achieved with 0.6 W CW output power and 60% power-added efficiency at 10 GHz. The thermal stabilization technique is applicable to other bipolar transistors including silicon, germanium, and indium phosphide devices. The disclosed fabrication sequence employs an improved two-step polyimide electrical isolation planarization sequence in preparation for fabrication of the thermal shunting element.

Growing community of inventors

Yellow Springs, OH, United States of America

Burhan Bayraktaroglu