Texas Instruments Corporation

Burhan Bayraktaroglu

Bumman Kim

William R Frensley

M Ali Khatibzadeh

Heterojunction bipolar transistors (130) with bases (138) including an etch stop element are disclosed. The preferred embodiment devices have Al.sub.x Ga.sub.1-x As emitters (140) and GaAs collectors (136) and bases (138) with In.sub.y Ga.sub.1-x As added to the bases (138) to stop chloride plasma etches.

Integrated circuit and method

Heterojunction bipolar transistors (130) with bases (138) including an etch stop element are disclosed. The preferred embodiment devices have Al.sub.z Ga.sub.1-z As emitters (140) and GaAs collectors (136) and bases (138) with In.sub.y Ga.sub.1-y As added to the bases (138) to stop chloride plasma etches.

Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter 108, a base 126 and a collector 24 is disclosed, wherein the base 126 is composed of one or more islands 126 of semiconductor material. The one or more islands 126 are formed so that they do not cross any boundaries of the active area 60 of the transistor.

Method for fabricating microwave heterojunction bipolar transistors

Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter, a base 50 and a collector 70 is disclosed, wherein the emitter composed of one or more islands 30 of semiconductor material having a wider energy bandgap than the base 50. The islands 30 are formed so that they do not cross any boundaries of the active area 60 of the transistor. Other devices, systems and methods are also disclosed.

Microwave heterojunction bipolar transistors suitable for low-power,

A monolithic circuit including an IMPATT with the IMPATT formed as a plurality of parallel vertical fingers or an array of vertical mesas having a common doped region to apread the area for heat dissipation through the substrate.

Interdigitated IMPATT devices

Preferred embodiments include a microstrip patch antenna (38) which also acts as the resonator for an oscillator powered by IMPATT diodes (34, 36); this forms a monolithic transmitter (30) for microwave and millimeter wave frequencies.

Monolithic microwave transmitter/receiver

Integrated circuits and fabrication methods incorporating both two-terminal devices such as IMPATT diodes (446) and Schottky diodes (454) and three-terminal devices such as n-channel MESFETs (480) in a monolithic integrated circuit.

A method of fabricating heterojunction bipolar transistors (HBTs) including epitaxial growth of collector, base and emitter layers, allowing for self-aligned emitter-base contacts to minimize series base resistance and to reduce total base-collector capacitance.

Self-aligned heterojunction bipolar transistor

This is a p-n junction device and the device comprises: a substrate 10 composed of a semiconductor material; a heavily doped n type sub-collector layer 14 over the substrate; a n type collector layer 16 over the sub-collector layer; a heavily doped p type first base layer 18, over the collector layer; a p type second base layer 20, substantially thinner than the first base layer, over the first base layer, with the second base layer being less heavily doped than the first base layer; and a n type emitter layer 24 over the second base layer, whereby, the second base layer serves as a diffusion barrier between the base and the emitter. Other devices and methods are also disclosed.

Method of making multilayer base heterojunction device having one of

Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter 108, a base 126 and a collector 24 is disclosed, wherein the base 126 is composed of one or more islands 126 of semiconductor material. The one or more islands 126 are formed so that they do not cross any boundaries of the active area 60 of the transistor. Other devices, systems and methods are also disclosed.

Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. Next, an i-layer 16 is grown over the first surface, over which an HFET electron donor layer 18 of the first conductivity type is grown, the electron donor layer 18 having a wider energy bandgap than the i-layer. Subsequently, an HFET contact layer 20 of the first conductivity type is grown over the HFET donor layer 18. Next, the HFET contact 20 and donor 18 layers are etched away over the HBT subcollector region 12, after which an HBT base layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base layer 22. Afterwards, an isolation region 30 is implanted at the boundaries between the HFET contact layer 20 and the HBT emitter layer 24/26/28, the isolation region 30 extending down into the substrate 10. Next, a portion of the HFET contact layer 20 is etched away to form an HFET gate contact recess. Lastly, conductive contacts 34, 44, 32, 36 and 40 are formed to the HFET contact layer 20, the HFET gate contact recess, the HBT emitter layer 24/26/28, the HBT base layer 22 and the HBT subcollector region 12.

Method of integrating heterojunction bipolar transistors with

Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. A PIN diode region 14 of the first conductivity type is then implanted in the substrate 10 at the first surface and spaced from the HBT subcollector region 12. Next, an i-layer 16 is grown over the first surface. Next, an HBT base/PIN diode layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12 and the PIN diode region 14. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base/PIN diode layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base/PIN diode layer 22. Afterwards, an isolation region 30 is implanted at the boundary between the HBT subcollector region 12 and the PIN diode region 14, the isolation region 30 extending down into the substrate 10. Next, the HBT emitter layer 24/26/28 is etched away over the PIN diode region 14. Lastly, conductive contacts 32, 36, 40, 38 and 42 are formed to the HBT emitter layer 24/26/28, the HBT base layer 22, the HBT subcollector region 12, the PIN diode layer 22 and the PIN diode region 14. Other devices, systems and methods are also disclosed.

Circuit integrating heterojunction bipolar transistors with pin diodes

Generally, and in one form of the invention, a p-n junction diffusion barrier is disclosed comprising a first semiconductor layer 28 of p-type conductivity, a second semiconductor layer 32 of n-type conductivity and a third semiconductor layer 30 of p-type conductivity disposed between the first and second layers, the third layer being doped with a relatively low diffusivity dopant in order to form a diffusion barrier between the first and the second semiconductor layers.

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Plano, TX, United States of America

Burhan Bayraktaroglu