Qualcomm Incorporated

Burcin Serter Ergun

Zhiqin Chen

Julian Puscar

Brett Patrick Delaney

Rakesh Kumar Sinha

Chiu Keung Tang

Raghav Gupta

Sajin Mohamad

Dewanshu Chhagan Sewake

Ashwith Jerome Rego

A voltage regulator includes a pass transistor coupled between an input and an output of the voltage regulator, and an amplifier having a first input configured to receive a reference voltage, and a second input coupled to the output of the voltage regulator via a feedback path. The voltage regulator also includes a voltage booster coupled between an output of the amplifier and a gate of the pass transistor, and a multiplexer having a first input configured to receive a first clock signal, a second input configured to receive a second clock signal having a higher frequency than the first clock signal, and an output coupled to a clock input of the voltage booster. The voltage regulator also includes a detection circuit having an input coupled to the amplifier, and an output coupled to a select input of the multiplexer.

Fast settled and transient low dropout (LDO) regulator

A system includes a voltage-controlled oscillator (VCO), a first second-order harmonic filter coupled to the VCO, wherein the first second-order harmonic filter includes a first tunable capacitor, and a second second-order harmonic filter coupled to the VCO, wherein the second second-order harmonic filter includes a second tunable capacitor. The system also includes a measurement circuit coupled to the VCO, wherein the measurement circuit is configured to measure a voltage swing of the VCO. The system also includes a control circuit coupled to the measurement circuit, the first tunable capacitor, and the second tunable capacitor.

Phase noise reduction for voltage-controlled oscillator using harmonic filter

A clock generation circuit has a voltage-controlled oscillator that includes a first transistor pair coupled in series between a power rail and ground, a replica transistor pair coupled in series between a reference node and ground, a current source having an output coupled to the reference node. The current source is coupled to a control signal that determines amplitude of current flowing through the replica transistor pair. A voltage regulator has an input coupled to the reference node and an output coupled to the power rail. The voltage regulator is configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. Each transistor in the replica transistor pair is collocated on an integrated circuit with and has a same type as a corresponding transistor in the first transistor pair.

Power supply calibration for voltage controlled oscillators

A method for calibrating a phase locked loop (PLL) includes counting cycles of an output clock signal generated by the PLL until early phase lock signal is asserted when the cycles of the output clock signal counted within a first duration of time differ from a first target value by no more than a first maximum difference, counting cycles of the output clock signal until final phase lock signal is asserted when the cycles of the output clock signal counted within a second duration of time differ from a second target value by no more than a second maximum difference, the second duration of time being greater than the first duration of time, and using the output clock signal to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.

Early lock detection for phase locked loops

A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

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Burcin Serter Ergun