Microsoft Technology Licensing, LLC

Bupesh Pandita

Charles Walter Boecker

Ping Lu

Minhan Chen

Anirban Banerjee

Eric Groen

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

Network transceiver with VGA channel specific equalization

Systems and methods related for duo-binary transceivers with adaptive channel equalization are described. An example method for adapting a channel between a first duo-binary transceiver and a second duo-binary transceiver, different from the first duo-binary transceiver, where the transmitter includes a feed-forward equalizer (FFE), is described. The method includes, at a receiver associated with the second duo-binary transceiver, selectively processing information at a given time from only an upper eye or a lower eye of a received duo-binary signal to determine updated coefficients for the feed-forward equalizer (FFE) of the transmitter associated with the first duo-binary transceiver. The method further includes using a backchannel between the transmitter and the receiver, sending the updated coefficients to the transmitter. The method further includes transmitting duo-binary signals that are equalized using the updated coefficients for the FFE of the transmitter associated with the first duo-binary transceiver.

Adaptive channel equalization for a duo-binary transceiver

In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.

Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods

A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.

Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods

Analog calibration (ACAL) circuits supporting iterative measurement of an input signal from a measured circuit, and related methods are disclosed. The ACAL circuit includes a voltage reference generation circuit and a comparator circuit. The voltage reference generation circuit is configured to provide an input reference voltage. The comparator circuit is configured to compare the input reference voltage to an input circuit voltage of a measured circuit and generate a digital measurement signal based on the comparison. To provide for the ACAL circuit to more precisely measure the input circuit voltage, the voltage reference generation circuit is programmable and is configured to a generate the input reference voltage based on a programmed reference voltage selection. In this manner, the ACAL circuit can be used to measure the input circuit voltage in an iterative manner based on different programmed input reference voltages for a more precise measurement of the input circuit voltage.

Programmable analog calibration circuit supporting iterative measurement of an input signal from a measured circuit, such as for calibration, and related methods

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Cary, NC, United States of America

Bupesh Pandita