Oki Semiconductor Co., Ltd.

Lapis Semiconductor Co., Ltd.

Oki Electric Industry Co., Ltd.

Zentel Japan Corporation

Bunsho Kuramori

Hiroyuki Tanikawa

Mineo Noguchi

Takashi Kubo

Masaru Haraguchi

Akihiro Hirota

Yuji Nagashima

Jun Setogawa

Hironori Iga

Daisuke Oda

Masahiro Ishihara

Mitsuru Yoneyama

Mitsunori Murakami

A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.

Semiconductor memory device for preventing occurrence of row hammer issue

A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder.

Nonvolatile semiconductor memory device and method of reusing same

There is provided a non-volatile storage device including: a memory array section arrayed with plural non-volatile memory cells for electronically writable data storage; plural bit lines that are connected to respective memory cells and have voltage levels that change according to the data stored in the memory cells; a supply section that supplies a voltage of a reference level to act as a comparator reference when determining data stored in the memory cells; a comparator section that compares the voltage level of the bit line connected to the memory cell subject to reading against the reference level supplied by the supply section; and a charging section that, in preparation for comparison by the comparator section, charges the bit line connected to the memory cell subject to reading to the voltage of the reference level supplied by the supply section.

Non-volatile storage device

There is provided a non-volatile storage device including: a bit line that is connected to a non-volatile storage element and is applied with a voltage of magnitude corresponding to the logic value stored in the storage element; a charging section that charges the bit line to a voltage of equivalent magnitude to the reference voltage; a voltage generation section that is connected between the reference voltage line and the bit line, comprises a capacitance load for generating coupling charge when charging by the charging section has been performed, and employs the capacitance load to generate a voltage according to a difference between the magnitude of the voltage of the reference voltage line and the magnitude of the voltage of the bit line as a voltage expressing the comparison result; and a charge absorbing section for absorbing the coupling charge generated by the capacitance load.

A semiconductor memory which is capable of performing data reading without a faulty operation irrespective of the span of an address skew period. In detecting whether an address transition has been made and precharging a bit line formed in a memory cell array when a certain delay period has elapsed after the address transition is detected, the delay period is adjusted based on a delay period extension signal.

Asynchronous semiconductor memory capable of preventing coupling noise

A nonvolatile memory includes a memory cell array having multiple memory cells, a read-out circuit outputting data stored in the memory cell array asynchronously in response to an input address signal, a selection circuit outputting a selection signal for selecting a location of the memory cell to fail, an error making circuit receiving a test mode signal, making the data outputted from the read-out circuit fail so that the failed data have an error, and outputting the failed data in response to the selection signal when the test mode signal is activated, and outputting the data outputted from the read-out circuit when the test mode signal is not activated, a data latch circuit latching either the failed data or the data outputted from the read-out circuit and outputting the latched data, and an error correcting circuit detecting the error in the latched data, correcting the error, and outputting the corrected signal.

Nonvolatile semiconductor memory and method of access evaluation to the same

A semiconductor memory device includes an array of memory cells and an adjustment circuit for adjusting the pulse width of an address transition detect equalizer (ATDEQ) signal. The adjustment circuit receives an address transition detection (ATD) signal and is responsive to the level changes of voltages Vp and Vn to adjust the pulse width of the ATDEQ signal accordingly. The resulting signal ATDEQ is supplied to a power supply circuit for a bit line selector for selecting a bit line of the array of memory cells. The device can thus accomplish the readouts of bit '0' and bit '1' in a state less liable to delay.

Delay circuit for controlling a pre-charging time of bit lines of a memory cell array

A substrate voltage generating circuit including level shifting circuits, a first power supply node of a first potential level Va second power supply node of a second potential level Vlower than the first potential level, and an output node OUT.vbb having a third potential level Vlower than the second potential level. The level shifting circuits are coupled between the first power supply node and the output node, receiving an input signal having the first and second potential levels, and outputting an output signal Vhaving the first potential level and the third potential level. The substrate voltage generating circuit also includes a switch circuit connecting the second power supply node to the output node in response to the output signal V

Substrate voltage generating circuit with improved level shift circuit

The present invention provides a delay circuit in which normal CMOS type inverters and modified inverters added with delay PMOSs on the power supply voltage VDD terminal side are alternately cascade-connected. A correction circuit that supplies a control signal to the gates of the delay PMOSs is provided in association with the delay circuit. The correction circuit comprises a PMOS diode-connected in the forward direction, and resistors that connect the drain of the PMOS to the ground voltage VSS terminal side. The correction circuit outputs the control signal from an internal node provided between the resistors. Thus, when a power supply voltage rises, the voltage of the control signal also rises. Hence, gate-to-source voltages of the delay PMOSs are kept constant, and drain currents remain unchanged and a delay time is kept constant as well.

Delay circuit having a correction circuit

A nonvolatile semiconductor memory for suppressing the access delay due to the parasitic capacitance between bit lines is disclosed. Bit lines are selected by a bit select signal, and the data of the memory cell selected in accordance with the level of data lines by a sense amplifier are read, after which the read data are held in a latch circuit. Then, a control signal is set to 'High', thereby to turn on a NMOS and set the data lines to a grounding potential. As a result, the charges of the selected bit lines are discharged. After that, even if adjacent bit lines are selected next for reading, the effect of the parasitic capacitance between the adjacent bit lines is obviated, and the next data can be read without causing any access delay.

Nonvolatile semiconductor memory

A nonvolatile memory includes a memory cell array in which a plurality of memory cells are connected to a plurality of wordlines and a plurality of bitlines respectively intersecting at a right angle with the plurality of wordlines; a selector for selecting one of the bitlines which is connected to first one of the memory cells in which actual data is stored; and a transfer circuit for connecting with a reference bitline which is connected to second one of the memory cells in which a reference level is stored. The nonvolatile memory further includes an amplifier section, connected to the selector and the transfer circuit, for reading out and amplifying levels of the bitline and the reference bitline and comparing the actual data with the reference level; and a charger for charging the bitline selected by the selector.

Electrically writable nonvolatile memory

A semiconductor integrated circuit comprises a plurality of memory cell blocks each including a comparing cell which detects a current level and data cells which store data therein, a plurality of reference voltage determining circuits each of which determines a second reference voltage in accordance with a first reference voltage and the output of the comparing cell, and amplifiers each of which compares the data stored in the data cell and the output of the reference voltage determining circuit and amplifies the result of comparison. The outputs of the comparing cells are short-circuited in a predetermined combination. Owing to the configuration of the semiconductor integrated circuit, misdetection of each reading cell due to process variations related to each individual comparing cell can be prevented and yield enhancement can be achieved. Further, such a configuration leads to a cost reduction.

Semiconductor integrated circuit

The aim of the present invention is to provide a power supply control system which enables an improvement in the response speed of the voltage sensor section to be achieved at a low level of power consumption. The present invention comprises: a voltage booster circuit for boosting voltage; a voltage sensor section which operates on the basis of voltage output from the voltage booster circuit; and a threshold value altering circuit which lowers a threshold value of the voltage sensor section when the voltage booster circuit is operating, and raises a threshold value of the voltage sensor section when the operation of the voltage booster circuit is halted.

Growing community of inventors

Tokyo, Japan

Bunsho Kuramori