Samsung Electronics Co., Ltd.

Bum-su Kim

Jong-Ho Park

Woo-Sik Kim

Chang-Won Choi

Shin-woo Nam

Dae-hyuk Chung

Ji-hwan Choi

Yeo-cheol Yoon

Sung-Uk Jung

Ki-chul Shin

A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.

Methods of manufacturing semiconductor devices having chamfered silicide layers therein

Semiconductor device having chamfered silicide layer and method for manufacturing the same

Liquid crystal displays are manufactured by securing overlying first and second substrates with an intermediate sealant together such that they form a cell cavity with an injection opening. In one embodiment, a plurality of over-sized spacers are disposed intermediate the first and second substrates in the cell cavity. The first and second substrates are structurally secured by heat compressing the layers together with a pressure in the range of about 0.4-0.55 kg/cm.sup.2. A quantity of liquid crystal material is injected into the cell cavity through the injection opening to expand the substrate layers to a non-planar configuration. A second sealant is applied proximate to the injection opening and a second compressing step is used to facilitate the proper positioning of the second sealant into injection opening. The second compressing step employs a pressure about 0.1-1.0 kg/cm.sup.2 greater than the pressure in the first compressing step. In one embodiment, the second compressing step is delayed by about 3-20 hours after the injecting step. In another embodiment, the over-sized spacers arc sized such that they are 10-30% larger than the cell cavity gap. The liquid crystal display includes first and second substrate layers and a first sealant which define a cell cavity and spacers in the cell cavity which are compressed by about 10-30% relative to their uncompressed configurations.

Liquid crystal displays and manufacturing methods thereof

Growing community of inventors

Kyungki-do, South Korea

Bum-su Kim