Samsung Electronics Co., Ltd.

Bum-Seok Yu

Woo-Hyun Lee

Jong-In Kim

Ji-Soo Kim

Yang-sup Lee

Jong-Keun Ahn

Kwang-Seok Im

Sang-Joo Ra

Disclosed is a solid state disk including a storage unit configured to store data, and a control part configured to control enciphering and writing operation for the data using a key value and an initialization vector. The initialization vector is generated by processing an address corresponding to the data.

Solid state disk and input/output method

A method of storing write data in flash memory incorporated in a storage device, the method includes; receiving write data and a logical block address (LBA) for the flash memory, determining whether the LBA exists in the cache memory, if the LBA exists in the cache memory, comparing the write data with cache data stored in the cache memory at a location associated with the LBA, and if the write data and the cache data are the same, terminating operation of the storage device without programming the write data to the flash memory, else updating an error detection information lookup table entry associated with the LBA and programming the write data to the flash memory, and if the LBA does not exist in the cache memory, updating the error detection information lookup table entry associated with the LBA and programming the write data to the flash memory.

Storage device with flash memory and data storage method

A storage apparatus including a storage unit to store data, a processor unit to process the data according to a command received from an external device, a key unit to store a plurality of crypto keys, and a decoder unit to select one of the crypto keys according to address information of the command received from the external device. Hardware encryption is more secure and less complex to manage.

Data storage apparatus having cryption and method thereof

A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.

Semiconductor disk devices and related methods of randomly accessing data

Provided is a memory controller configured to control a flash memory device. The memory controller includes: a buffer memory configured to store data to be written in the flash memory device; a buffer memory interface configured to control read and write operations of the buffer memory; and an automatic command processing unit configured to interpret a data command generated by a host hardware device.

Memory controller with automatic command processing unit and memory system including the same

The present invention relates to a synchronizing circuit for stably generating an output signal irrespective of the frequency difference of clocks. According to the present invention, the synchronizing circuit receives an input signal synchronized with a first clock and then stores a state of the input signal so that the input signal is synchronized with a transition of a second clock. then, the synchronizing circuit generates an output signal synchronized with the transition of the second clock. In addition, an input signal synchronized with the first clock becomes synchronized with the second clock having a lower frequency than the first clock.

Synchronizing circuit for stably generating an output signal

A microcontroller includes an electrically erasable and programmable nonvolatile memory and a memory controller for controlling the nonvolatile memory. Upon writing a control program for the microcontroller and data into the nonvolatile memory pursuant to an externally provided NVM command or an internally issued program command, a CPU of the microcontroller does not intervene in controlling the nonvolatile memory. Particularly, in a programming mode set by the external program command, CPU, buses, and communication interfaces of the microcontroller are deactivated. Further, the memory controller receives a NVM command, an address and data from outside of the microcontroller for controlling an operation of the nonvolatile memory based on the NVM command and the address without intervention of the CPU.

Growing community of inventors

Suwon-si, South Korea

Bum-Seok Yu