Samsung Electronics Co., Ltd.

Bum-seok Seo

Jung-hyun Lee

June-mo Koo

Sung-ho Park

Myoung-jae Lee

Ki-Joon Kim

Sang-Jun Choi

Kil-Ho Lee

Yoon-Dong Park

Sun-ae Seo

Chang-soo Lee

Kyoung-won Na

Deok-kee Kim

Dong-seok Suh

Young-Kwan Cha

Seok-Han Park

Hyung-jin Bae

Jong-Pyo Kim

Jung-Hyoung Lee

Sang-Bong Bang

Ju-chul Park

Jeong-seop Shim

Provided is a method of forming fine patterns, which is capable of easily forming a plurality of patterns repeatedly with a fine pitch when forming patterns necessary for manufacturing a highly integrated semiconductor device exceeding a resolution limit of a photolithography process.

Method of forming fine patterns

An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

Methods of forming patterns and methods of manufacturing semiconductor devices using the same

Provided is a non-volatile memory device including at least one horizontal electrode, at least one vertical electrode, at least one data storage layer and at least one reaction prevention layer. The least one vertical electrode crosses the at least one horizontal electrode. The at least one data storage layer is located in regions in which the at least one vertical electrode crosses the at least one horizontal electrode, and stores data by varying its electrical resistance. The at least one reaction prevention layer is located in the regions in which the at least one vertical electrode crosses the at least one horizontal electrode.

Non-volatile memory device with data storage layer

Provided are an organic-metal precursor material that can be readily decomposed without reacting with an oxidant, a method of manufacturing a metal thin film using the organic-metal precursor material, and a metal thin film prepared using the organic-metal precursor material. The organic-metal precursor material is an organic molecule having lone-pair electrons selected from the group consisting of ether, amine, tetrahydrofuran (THF), a phosphine group, and a phosphite group, and has a structure of covalent coordination bond.

Organic-metal precursor material and method of manufacturing metal thin film using the same

A method of forming carbon fibers at a low temperature below 450&#xb0; C. using an organic-metal evaporation method is provided. The method includes: heating a substrate and maintaining the substrate at a temperature of 200 to 450&#xb0; C. after loading the substrate into a reaction chamber; preparing an organic-metal compound containing Ni; forming an organic-metal compound vapor by vaporizing the organic-metal compound; and forming carbon fibers on the substrate by facilitating a chemical reaction between the organic-metal compound vapor and a reaction gas containing ozone in the reaction chamber.

Method of forming carbon fibers using metal-organic chemical vapor deposition

Example embodiments relate to a method of manufacturing amorphous NiO thin films and nonvolatile memory devices including amorphous thin films that use a resistance material. Other example embodiments relate to a method of manufacturing amorphous NiO thin films having improved switching and resistance characteristics by reducing a leakage current and non-volatile memory devices using an amorphous NiO thin film. Provided is a method of manufacturing an amorphous NiO thin film having improved switching behavior by reducing leakage current and improving resistance characteristics. The method may include preparing a substrate in a vacuum chamber, preparing a nickel precursor material, preparing a source gas by vaporizing the nickel precursor material, preparing a reaction gas, preparing a purge gas and forming a monolayer NiO thin film on the substrate by performing one cycle of sequentially supplying the source gas, the purge gas, the reaction gas and the purge gas into the vacuum chamber.

Method of manufacturing amorphous NiO thin films and nonvolatile memory devices using the same

Provided are a Ge precursor for low temperature deposition containing Ge, N, and Si, a GST thin layer doped with N and Si formed using the same, a memory device including the GST thin layer doped with N and Si, and a method of manufacturing the GST thin layer. The Ge precursor for low temperature deposition contains N and Si such that the temperature at which the Ge precursor is deposited to form a thin layer, particularly, the GST thin layer doped with N and Si, can be low. In addition, during the low temperature deposition, Hplasma can be used. The GST phase-change layer doped with N and Si formed from the Ge precursor for low temperature deposition has a low reset current. Therefore, a memory device including the GST phase-change layer doped with N and Si can be highly integrated, have a high capacity, and can be operated at a high speed.

Ge precursor, GST thin layer formed using the same, phase-change memory device including the GST thin layer, and method of manufacturing the GST thin layer

A nonvolatile variable resistance memory device may include a lower electrode; a stacked structure including a first Cu compound layer disposed on the lower electrode, and a second Cu compound layer disposed on the first Cu compound layer; and an upper electrode disposed on the second Cu compound layer.

Nonvolatile variable resistance memory device and method of fabricating the same

A conductive carbon nanotube tip and a manufacturing method thereof are provided. The conductive carbon nanotube tip includes a carbon nanotube tip substantially vertically placed on a substrate, and a ruthenium coating layer covering a surface of the carbon nanotube tip and extending to at least a part of the substrate. The manufacturing method includes substantially vertically placing a carbon nanotube tip on a substrate, and forming a ruthenium coating layer on the carbon nanotube tip and at least a part of the substrate.

Conductive carbon nanotube tip, probe having the conductive carbon nanotube tip, and method of manufacturing the conductive carbon nanotube tip

A capacitor having a dielectric layer including a composite oxide, the composite oxide including a transition metal and including a lanthanide group element, a memory device including the same and a method of manufacturing the capacitor are provided. The transition metal may be titanium and the composite oxide may be nitrided. The method may include providing a precursor of a transition metal, providing a precursor of a lanthanide group element, and forming a composite oxide on the lower electrode by oxidizing both the precursor of the transition metal and the precursor of the lanthanide group element, the composite oxide containing the transition metal and the lanthanide group element.

Capacitor having a dielectric layer that reduces leakage current and a method of manufacturing the same

Methods of fabricating a lanthanum oxide layer, and methods of fabricating a MOSFET and/or a capacitor especially adapted for semiconductor applications using such a lanthanum oxide layer are disclosed. The methods include a preliminary step of disposing a semiconductor substrate into a chamber. Tris(bis(trimethylsilyl)amino)Lanthanum as a lanthanum precursor is then injected into the chamber such that the lanthanum precursor is chemisorbed on the semiconductor substrate. Then, after carrying out a first purge of the chamber, at least one oxidizer is injected into the chamber such that the oxidizer is chemisorbed with the lanthanum precursor on the semiconductor substrate. Then, the chamber is purged a second time. The described steps of injecting the lanthanum precursor into the chamber, first-purging the chamber, injecting an oxidizer into the chamber, and second-purging the chamber may be sequentially and repeatedly performed to form a lanthanum oxide layer of a desired thickness having enhanced semiconductor characteristics.

Method of fabricating lanthanum oxide layer and method of fabricating MOSFET and capacitor using the same

A capacitor of a semiconductor device includes a lower electrode, a dielectric layer, including a plurality of band gaps, formed on the lower electrode, and an upper electrode formed on the dielectric layer. A band gap of the plurality of band gaps in the dielectric layer that is not adjacent to either the lower electrode or the upper electrode is smaller than a band gap of the plurality of band gaps in the dielectric layer adjacent to the lower electrode and a band gap of the plurality of band gaps in the dielectric layer adjacent to the upper electrode.

Growing community of inventors

Yongin-si, South Korea

Bum-seok Seo