International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Bulent Abali

Hubertus Franke

Bartholomew Blaner

Mohammad Banikazemi

Dan Edward Poff

Alper Buyuktosunoglu

John J Reilly

Luis Alfonso Lastras-Montano

Michael R Hines

Makoto Ono

Ashutosh Misra

Paul Gregory Crumley

Matthias Klein

Gokul Bhargava Kandiraju

Balaram Sinharoy

Brian Robert Prasky

Chung-Sheng Li

James Lee Hafner

Jeffrey Owen Kephart

Deanna Postles Dunn Berger

Canturk Isci

Girish Gopala Kurup

James Anthony Marcella

Dipankar Das Sarma

Suzanne K McIntosh

Jack Lawrence Kouloheris

Michele M Franceschini

Erich Miles Nahum

Mark Edwin Giampapa

Damir Anthony Jamsek

Thai Franck Le

Kenneth Anthony Lauricella

Luis A Lastras

Krishnakumar Rao Surugucchi

Michael M Tsao

Deepankar Bhattacharjee

Dorothy Marie Thelen

Robert A Saccone, Jr

Craig B Agricola

John Steven Dodson

Jeffrey A Stuecheli

Timothy Joseph Chainer

John Peter Karidis

Ashish Jagmohan

John Alan Bivens

David Darden Chambliss

Peter Anthony Franaszek

Ganesh Balakrishnan

Joseph S Glider

Peter Anthony Sandon

Michael B Healy

Seetharami R Seelam

Livio B Soares

Moinuddin K Qureshi

Craig Brian Stunkel

Aruna V Ramanan

Cameron James Mcallister

D Scott Guthridge

Ashutosh Mishra

Prashant Jayaprakash Nair

Marcio Augusto Silva

Seokin Hong

Suneel Pusarla

Steven M Wheeler

William John Starke

Pradip Bose

Eren Kursun

Michael Stephen Floyd

John Michael Borkenhagen

Cedric Lichtenau

Christoph Raisch

Pratap Chandra Pattnaik

Richard Edwin Harper

Ronald Mraz

Sameh W Asaad

Marco Kraemer

Lorraine M Herger

Guerney D H Hunt

Charles Otto Schulz

Linda Ann Riedle

Preetham M Lobo

Karthik V Swaminathan

Jang-Soo Lee

Kevin J Reilly

Gary Valentin

Rajat Rao

James W Arendt

T Basil Smith, Iii

Peter Alexander Manson

Ziv Rafalovich

Daniel Edward Poff

Krishankumar Rao Surugucchi

Harry B Marr, Jr

Nancy M Wei

Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes ('ECC') and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.

Location-aware protection system of latches (LAPS-L)

A method to handle insufficient on-chip memory capacity in decompressors is disclosed. In one embodiment, such a method includes executing, by a decompressor configured to decompress data, an instruction configured to copy data from a source position within a data stream to a destination position within the data stream. The method determines whether the source position currently resides within an on-chip buffer of the decompressor. In the event the source position does not currently reside within the on-chip buffer of the decompressor, the method writes arbitrary placeholder data to the destination position and adds the instruction to a patch buffer. At a later point in time, the method retrieves the instruction from the patch buffer and executes the instruction by retrieving the data from the source position and overwriting the arbitrary placeholder data at the destination position with the data. A corresponding system and computer program product are also disclosed.

Technique to handle insufficient on-chip memory capacity in decompressors

Trustworthiness of an accelerator in heterogenous systems is increased. A workload of an application is offloaded to an accelerator for the accelerator to perform the workload. The accelerator is ensured to generate an output of the workload based on offloading the workload. The accelerator is identified as generating an output of the workload based on offloading the workload. Both an input and the output of the workload are ensured to be authentic based on offloading the workload to the accelerator. Both the input and the output of the workload are ensured to be securely transmitted based on offloading the workload to the accelerator.

Accelerator trustworthiness

A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.

Cache line compression prediction and adaptive compression

A first type memory and a second type memory may be identified in a computing system. The second type memory is slower than the first type memory while having a greater storage capacity compared to the first type memory. An application process executing in the computing system may be identified. A region of the first type memory may be provided as a cache of the second type memory for the application process.

Providing a dynamic random-access memory cache as second type memory per application process

An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes receiving an input/output (I/O) transaction from an I/O device requesting data stored memory from a virtual machine. The I/O transaction includes a virtual memory address and a bus device function. The method also includes associating the I/O transaction with a key slot associated with the virtual machine and retrieving, using the key slot, an encryption key used to encrypt and decrypt the data. The method further includes retrieving the data located at a physical memory address in physical memory relating to the virtual memory address of the data being requested and decrypting, during a read operation, the data using the encryption key for I/O transmission. The method also includes transmitting the decrypted data to the I/O device.

Secure communication of virtual machine encrypted memory

Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

Computation and placement of error correcting codes (ECC) in a computing system data cache

An intrusion detection and recovery system includes a copying module that creates a point-in-time copy of a storage level logical unit, the point-in-time copy including a volume copy of the storage level logical unit and signatures of the storage level logical unit, a comparison module that compares at least a portion of the point-in-time copy with a previous copy of the storage level logical unit, a judging module that, based on results of the comparison module, judges if a modification has occurred. A signature of the point-in-time copy is compared with a signature of the previous copy to detect a sign of an intrusion. The signatures of the storage level logical unit include encoded data of files of the storage level logical unit that are monitored in the point-in-time copy.

Method and system for storage-based intrusion detection and recovery

A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.

Multi purpose server cache directory

Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.

Fast clear memory of system memory

Embodiments include performing decompression of a file. Aspects include receiving a compressed input stream for the file and processing the compressed input stream, by two or more pipelines in parallel, to create an output vector, wherein each pipeline includes a first decoder and a second decoder. Aspects also include writing, by each of the two or more pipelines, entries onto a scratchpad in an order defined by the output vector and writing one or more entries from the scratchpad to a main history buffer based on a determination that a validity field of the one or more entries has a value of true.

Decompression of a file

Data may be transferred from a volatile memory to a non-volatile memory using a persistent power enabled on-chip data processor upon detecting a power loss from a primary power source. The one or more emergency power supplies are attached to the volatile memory, the non-volatile memory, and the persistent power enabled on-chip data processor to assist with the transferring of data.

Persistent power enabled on-chip data processor

A method, system, and computer program product for local DRAM caching of storage class memory elements are provided. The method identifies a cache line with a cache address in a local dynamic random-access memory (DRAM). The cache line is compressed within the local DRAM to generate a compressed cache line and an open memory space within the local DRAM. A cache tag is generated in the open memory space and a validation value is generated in the open memory space for the compressed cache line. The method determines a cache-hit for the cache line based on the cache address, the cache tag, and the validation value.

DRAM caching storage class memory

Low latency in a non-uniform cache access ('NUCA') cache in a computing environment is provided. A first compressed cache line is interleaved with a second compressed cache line into a single cache line of the NUCA cache, where data of the first compressed cache line is stored in one or more even sectors in the single cache line and stored in zero or more odd sectors in the single cache line after the data fills the one or more even sectors, and data of the second compressed cache line is stored in the one or more odd sectors in the single cache line and stored in zero or more even sectors in the single cache line after the data fills the one or more odd sectors.

Transparent interleaving of compressed cache lines

Various embodiments are provided for enabling data compression in a computing system by a processor. Each storage block of a storage device associated with a queue may be split. Compression of data may be activated upon data occupancy within a queue exceeding a dynamic threshold. In one aspect, only a partial amount of the data is fetched, back to back, from a divided storage block in the storage block according to the queue based upon the data occupancy within the queue exceeding the dynamic threshold. A complete amount of the data may be fetched from the divided storage block in a storage block according to the queue upon the data occupancy within the queue being less than dynamic threshold.

Enabling compression based on queue occupancy

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Tenafly, NJ, United States of America

Bulent Abali