Psemi Corporation

Peregrine Semiconductor Corporation

Murata Manufacturing Co., Ltd.

Buddhika Abesingha

Merlin Green

Arezu Bagheri

Gregory Szczeszynski

Simon Edward Willard

Ronald Eugene Reedy

Alain Duvallet

Sivakumar Kumarasamy

Mark L Burgener

James W Swonger

Gary Chunshien Wu

Tim Wen Hui Yu

Keith J Rampmeier

Methods and devices for a cascode current mirror with low headroom voltage are presented. According to one aspect, a gate voltage to a cascode transistor of an input leg of the current mirror is provided by a feedback block that operates from a mirrored current output by an output leg of the current mirror. The feedback block includes a feedback current mirror that outputs a mirrored current for conduction through a self-biasing diode-connected transistor that generates the gate voltage to the cascode transistor of the input leg. According to yet another aspect, the cascode current mirror includes a start-up circuit coupled between an input to the input leg and a gate of the cascode transistor of the input leg, the start-up circuit generating a start-up voltage during a transition mode of operation of the cascode current mirror. According to one aspect, a transistor is used as the start-up circuit.

Low voltage cascode current mirror

A switching power converter architecture that is efficient across its entire power range, regardless of load level, by partitioning the power devices into segments for optimal gate drive and providing a local variable-voltage driver for each power device segment. Power device segments may be selectively enabled or disabled based on the level of power to be delivered to a load. In addition, an adaptive gate drive scheme enables dynamic control of the Rand Qvalues for each power converter device so that the power devices may operate at the lowest Rvalue at or near maximum power levels for reduced conduction losses, at the lowest R×Qproduct value at mid-level loads for peak efficiency, and at the lowest Qvalue at light loads for reduced switching losses.

Power converter with adaptative stages and gate driver

A power converter includes a charge pump in which transistors transition between conducting and non-conducting states thereby causing said pump capacitors to be interconnected in different arrangements at different times. Among the transistors is one that transitions into a conducting state when a source and gate of that transistor are at equal potentials.

Driving circuit for switches used in a charge pump

Methods and devices for sensing current through a power converter circuit are presented. According to one aspect, currents through high-/low-side transistors are sensed via respective reduced size replica transistors. According to another aspect, the sensed currents are used to generate bridging currents that are combined with the sensed currents to generate a continuous current sense signal. According to another aspect, the bridging currents include slopes that are generated from slopes of the sensed currents. According to another aspect, the sensed currents are combined and filtered to generate a continuous sense signal. According to another aspect, the continuous current sense signal is a voltage that is compared to a reference voltage to generate a current limit status flag used to control operation of the power converter circuit. According to other aspects, the current sense voltage is used to control ON/OFF duty cycle of the power converter circuit.

Circuits and methods for generating a continuous current sense signal

Methods and devices to decrease the power consumption of level shifters in the absence of input power supply are disclosed. The described devices include current mirrors that are inactive when the level shifter is in the HIGH or LOW steady state. The disclosed methods further include a delay element used to keep the power consumption low in the case of slow input power supply ramps.

Low power level shifter

Disclosed embodiments may include a power converter having a power conversion circuit and a protection circuit. The power conversion circuit is electrically coupled between a first terminal and a second terminal, to convert a first voltage from the first terminal to a second voltage outputted at the second terminal. The protection circuit is electrically coupled between an input terminal of the power converter and the first terminal. The protection circuit includes a first protection device and a clamping circuit. The first protection device withstands an input voltage of the power converter to continue an operation of the power conversion circuit when the input voltage exceeds a voltage threshold value. The clamping circuit is electrically coupled to a control terminal of the first protection device to clamp a control voltage of the first protection device.

Power converters, power systems, and methods for protecting power converters

Circuits and methods for transmitting high-voltage (HV) static and/or switching signals via a high-voltage (HV) transmission gate controllable via low-voltage (LV) logic are presented. The HV gate includes a biasing circuit for generating a biasing voltage to gates of two series-connected HV transistors. According to one aspect, the biasing voltage is generated through a pull-up device coupled to a HV supply having a voltage level higher than a high voltage of a signal to be transmitted. According to another aspect, the biasing voltage is generated through a LV supply coupled to a diode, and a capacitor coupled between the gates and the sources of the HV transistors. When the gate is activated, the combination of the LV supply coupled to the diode and the capacitor generates a biasing voltage based on a sum of a voltage of the LV supply and an instantaneous voltage level of the signal being transmitted.

High-voltage transmission gate architecture

Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During the standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back-gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During the standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.

Circuits and methods for leakage reduction in MOS devices

Systems, methods, and devices for accurate sensing of gate voltages of high-voltage devices are presented. A gate sense circuit can generate accurate transitions of the gate voltages via a differential input provided by a gate node voltage and a source node voltage of the high-voltage devices. The differential input is fed to two separate processing paths, one path for accurate detection of a rising edge of the gate voltage with a reduced propagation delay, and the other path for accurate detection of a falling edge of the gate voltage with a reduced propagation delay. A switch selects an output of the two paths that accurately detects a next edge to be detected. An Output pulse signal defined by the detected rising and falling edges is generated based on the output of the switch.

Accurate high-voltage gate detector

Methods and devices to address start up of half-bridge circuits including D-mode power FETs are disclosed. The disclosed devices overcome possible issues of output overload or excess current through gate-source of power FETs during start up. Voltage monitoring is used to address the issue of output overload and pre-charging of coupling capacitors are described as solutions to uncontrolled pre-charging of coupling capacitors. Pre-charging of coupling capacitors are implemented using current sources.

Reliability in start up sequence for D-mode power FET driver

Methods and devices to address start up of half-bridge circuits including D-mode power FETs are disclosed. The disclosed devices overcome possible issues of output overload or excess current through gate-source of power FETs during start up. Methods and devices based on monitoring coupling capacitors voltages and pre-charging such coupling capacitors using current sources are also described. The current sources can be implemented using negative voltages provided by negative voltage sources such as charge pumps.

Systems, methods, and devices for generation of narrow pulses in a flying high-voltage domain that are used as a timing control signal are presented. A main signal processing path that generates the timing control signal is replicated and used to detect time and duration of perturbations due to flying events in the main signal processing path based on a fixed input level to the replicated path. Detected time and duration of the perturbations are used to generate a blanking control signal to the main signal processing path. According to one aspect, the main signal processing path may be part of a high side level shifter that operates in a flying high-voltage domain and used to control a high-voltage switching device.

Flying level shifter for narrow pulses

Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.

Systems, methods, and apparatus for enabling high voltage circuits

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.

Growing community of inventors

Escondido, CA, United States of America

Buddhika Abesingha