Samsung Electronics Co., Ltd.

Bub-chul Jeong

Jaegeun Yun

Lingling Liao

Sung-Min Hong

Hyun-Joon Kang

Jae-Geun Yun

Junhyung Um

Jae Geun Yun

Jae Gon Lee

Jun Hee Yoo

Dongsoo Kang

Sung-Hyun Lee

Woo Cheol Kwon

Jun-Hee Yoo

Hyunuk Jung

Sunghoon Shim

Woo-Cheol Kwon

Soo Wan Hong

Jun Hyung Um

Jung-Sik Lee

Ling Ling Liao

A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Clock gating circuit

A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.

System interconnect and operating method of system interconnect

Bus system in SoC

A system on chip (SOC) includes a slave device, a plurality of master devices, an interconnect device and a plurality of service controllers. The master devices generate requests to demand services from the slave device. The interconnect device is coupled to the slave device and the master devices through respective channels, and the interconnect device performs an arbitrating operation on the requests. The service controllers control request flows from the master devices adaptively depending on an operational environment change of the SOC.

Adaptive service controller, system on chip and method of controlling the same

A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The master devices generate requests to demand services from the slave device, respectively. The service controllers generate urgent information signals and priority information signals for each of the master devices. The interconnect device is coupled to the slave device and the master devices through respective channels. The interconnect device performs an arbitrating operation on the requests based on the priority information signals and controls request flows between the slave device and the master devices based on the urgent information signals.

System on chip for enhancing quality of service and method of controlling the same

A backbone channel transmits first through third channel packets among Advanced eXtensible Interface (AXI) 5 channel packets. The backbone channel is managed by dividing the backbone channel into a first sub-channel and a second sub-channel, transmitting the first channel packet through the first sub-channel, transmitting the second channel packet through the second sub-channel, and transmitting the third channel packet through both the first sub-channel and the second sub-channel.

Backbone channel management method and backbone channel management apparatus

An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.

Asynchronous bridge

Bus system in SoC and method of gating root clocks therefor

A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the slave device.

Bus system including a master device, a slave device, an interconnector coupled between the master device and the slave device, and an operating method thereof

A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.

System on chip improving data traffic and operating method thereof

An interface device includes a request queue and a request queue manager. The request queue includes multiple elements configured to receive corresponding requests from at least one master device and to indicate whether the corresponding requests are included using corresponding occupying bits. The request queue manager is configured to manage the request queue at least based on the occupying bits.

Interface device and system including the same

A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.

System on chip comprising interconnector and control method thereof

A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.

System-on-chip and data arbitration method thereof

A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the salve device.

Bus-system including an interconnector, a master device, a slave device, and an operating method thereof

Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.

Growing community of inventors

Yongin-si, South Korea

Bub-chul Jeong