Samsung Electronics Co., Ltd.

Bu-il Jung

Hyun-Joong Kim

Ho-young Song

Ju-yun Jung

Sang-hoon Shin

Myung-Gyoo Won

Kyo-min Sohn

Hae-suk Lee

Soo-hyeong Kim

Han-vit Jeong

A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

Memory device having a shareable error correction code cell array

A memory device includes a bit line sense amplifier, a command decoder configured to generate an internal control signal indicating an operating mode of the memory device, and a bit line sense amplifier controller configured to selectively apply an external voltage as a supply voltage to the bit line sense amplifier in response to the internal control signal.

Memory device for retaining data during power-down mode and method of operating the same

Growing community of inventors

Gyeonggi-do, South Korea

Bu-il Jung