Samsung Electronics Co., Ltd.

Bu-Il Jung

Dong-Yang Lee

Ju-yun Jung

Min-Yeab Choo

So-Young Kim

Sun-Young Lim

Do-Geun Kim

Hyuk Soo Han

Mi-Kyoung Park

Sung-Ho Cho

Hee-Joo Choi

A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.

Memory system capable of re-mapping address

A semiconductor memory system or device includes a memory cell array and an address converter. The memory cell array includes a plurality of memory blocks, and there is at least one block that serves as a buffer. Each of the memory blocks includes at least one memory cell row. An address converting circuit along with a block copy circuit performs a block copy operation of copying data of a first memory block, which is a source block among the memory blocks, into a second block, which is a buffer or destination block, and maps a first logical address for accessing the first memory block onto a physical address designating the second block. The first memory block then can serve as a new destination block after the block copy operation of the first memory block is completed.

Semiconductor memory device and memory system

A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.

Memory device and computing system including the same

A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.

Method of repairing a memory device and method of booting a system including the memory device

A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal.

Refresh address generator, volatile memory device including the same and method of refreshing the volatile memory device

A memory device comprises a normal storage area comprising first and second subsets configured to store first and second normal data, respectively, an error code storage area configured to store first and second error codes corresponding to the first and second normal data, an error detector configured to receive the first and second normal data and the first and second error codes, and further configured to detect the presence or absence of one or more errors in the first and second normal data or the first and second error codes, and a refresh controller configured to set respective refresh cycle times of the first and second subsets to different values according to the presence or absence of one or more errors in the first and second normal data or error codes.

Memory device having reconfigurable refresh timing

The apparatus may include a non-pumping power supply unit configured to generate a supply voltage from a power source voltage and/or configured to output the supply voltage. The apparatus may include a pumping power supply unit and/or a control circuit. The pumping power supply unit may be configured to generate a pump voltage based on the power source voltage and/or configured to output the pump voltage. The control circuit may boost the supply voltage with the pump voltage after a level of the supply voltage reaches the first target voltage level.

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Hwaseong-si, South Korea

Bu-Il Jung