Rockwell Collins, Inc.

Rockwell International Corporation

Bryon L Wiscons

Mark A Kovalan

John L Persick

Douglas Robert Johnson

Stephen I Kotalik

Gregory E Dunn

Ronald W Aull

Jimmie L Fisher

A data transfer mechanism for directing data signals from signal-producing elements to signal-receiving elements is disclosed. The data transfer mechanism includes a plurality of input ports, with each input port being connected to a signal-producing element, and a plurality of output ports, with each output port being connected to a signal-receiving element. Each data signal that enters the data transfer mechanism through one of the plurality of input ports has data identification information associated therewith. The, data transfer mechanism directs the data signal to at least one of the plurality of output ports according to the data identification information associated with the data signal.

Flexible I/O subsystem architecture and associated test capability

A bus system including a bus user apparatus and a method for communicating via the bus system are disclosed. The bus user apparatus includes means for means for selectively coupling a transmitter to the transmission line according to a protocol of the bus system. The bus system provides bi-directional communication over a single transmission line. The transmitter of the transmitting device is coupled to the transmission line during transmission. Upon completion of transmission, the transmitting device sends a permission to transmit signal to the next transmitting device according to the protocol, and decouples its transmitter from the transmission line. The next transmitting device couples its transmitter to the transmission line and begins transmission of data. Multiple bus users, both transmitters and receivers, are accommodated by the bus system, and bi-directional communication is supported. Further, the data transmission rate may be increased by selectively coupling the transmitter of a receiving device to the transmission line to provide a termination impedance on the transmission line. Higher transmission rates may be accommodated without a termination impedance; if necessary, a termination impedance may be applied. If necessary, the output voltage of the transmitter and the sensitivity of the receiver may be adjusted to accommodate the higher transmission rates. The bus system may also accommodate larger sized words. The bus system is compatible with previously existing systems compliant with an ARINC standard while providing increased capability.

Data bus

A circuit and technique of operation thereof are disclosed for a multimaster CPU system wherein a memory may be accessed during program operation in an average time less than that of the memory access time specification. This technique has particular usefulness in programs contained in relatively slow read-only-memory wherein a significant portion of the addresses related to memory are sequential. In optimum utilization, each master CPU has a dedicated PROM card which can only be enabled by the specified CPU. This configuration prevents additional master CPU's from interfering with the time saving benefits of early memory addressing.

Multimaster CPU system with early memory addressing

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Marion, IA, United States of America

Bryon L Wiscons