Advanced Micro Devices Corporation

Bryon I Moyer

Bradley A Sharpe-Geisler

Nicholas A Schmitz

Om P Agrawal

John David Porter

Jeffery Mark Marshall

Benjamin Howard Ashmore, Jr

A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.

Block clock and initialization circuit for a complex high density PLD

For each programmable logic block in a programmable logic device, a programmable power and speed control circuit is programmably configurable to generate an output signal on a power and speed control line so that the static power consumption of the corresponding programmable logic block is adjusted to provide a particular combination of power and speed for that programmable logic block, i.e., a specific power/speed performance point. For each programmable logic block in the programmable logic device, a plurality of programmable selectable speed/power levels are provided by the programmable power and speed control circuit. This allows a distribution of programmable logic blocks in the programmable logic device that are powered to various performance levels to match more closely a distribution of performance requirements by the circuit that includes the various programmable logic blocks.

Programmable logic device with multi-level power control

A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchial level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.

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Cupertino, CA, United States of America

Bryon I Moyer